Two-Dimensional Si Spin Qubit Arrays with Multilevel Interconnects
Sieu D. Ha, Edwin Acuna, Kate Raach, Zachery T. Bloom, Teresa L. Brecht, James M. Chappell, Maxwell D. Choi, Justin E. Christensen, Ian Thomas Hunt Counts, Dominic Daprano, J.P. Dodson, Kevin Eng, David J. Fialkow, Christina A. C. Garcia, Wonill Ha, Thomas R. B. Harris, Nathan Holman, Isaac Khalaf, Justine W. Matten, Christi A. Peterson, Clifford E. Plesha, Matthew J. Ruiz, Aaron Smith, Bryan J. Thomas, Samuel J. Whiteley, Thaddeus D. Ladd, Michael P. Jura, Matthew T. Rakher, Matthew G. Borselli
The promise of quantum computation is contingent upon physical qubits with both a low gate error rate and broad scalability. Silicon-based spins are a leading qubit platform but demonstrations to date have not utilized fabrication processes capable of extending arrays in two dimensions while maintaining complete control of individual spins. Here, we implement an interconnect process, common in semiconductor manufacturing, with multiple back-end-of-line layers, to show an extendable two-dimensional array of spins with fully controllable nearest-neighbor exchange interactions. In a device using three interconnect layers, we encode exchange-only qubits and achieve average single-qubit gate fidelities consistent with single-layer devices, including fidelities greater than 99.9%, as measured by blind randomized benchmarking. Moreover, with spin connectivity in two dimensions, we show that both linear and right-angle exchange-only qubits with high performance can be formed, enabling qubit array reconfigurability in the presence of defects. This extendable device platform demonstrates that industrial manufacturing techniques can be leveraged for scalable spin qubit technologies.
The promise of quantum computation is contingent upon physical qubits with both a low gate error rate and broad scalability. Silicon-based spins are a leading qubit platform but demonstrations to date have not utilized fabrication processes capable of extending arrays in two dimensions while maintaining complete control of individual spins. Here, we implement an interconnect process, common in semiconductor manufacturing, with multiple back-end-of-line layers, to show an extendable two-dimensional array of spins with fully controllable nearest-neighbor exchange interactions. In a device using three interconnect layers, we encode exchange-only qubits and achieve average single-qubit gate fidelities consistent with single-layer devices, including fidelities greater than 99.9%, as measured by blind randomized benchmarking. Moreover, with spin connectivity in two dimensions, we show that both linear and right-angle exchange-only qubits with high performance can be formed, enabling qubit array reconfigurability in the presence of defects. This extendable device platform demonstrates that industrial manufacturing techniques can be leveraged for scalable spin qubit technologies.
Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300~mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times T2∗ up to 41(2)μs and Hahn-echo coherence times T2Hahn up to 1.31(4)ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.
Utility-scale quantum computing requires the integration and operation of a large-scale qubit register. Semiconductor spin qubits are a primary candidate for this, due to the prospects of building integrated hybrid quantum-classical architectures. However, scaling spin-qubit systems while preserving performance and control has remained a challenge. Here, we demonstrate the operation of an 18-qubit array in germanium based on an extendable 2xN architecture. We achieve simultaneous initialization, control, and readout across the entire array, enabled by parallel operation of modular unit cells. Across the array, we achieve average and median single-qubit gate fidelities of 99.8% and 99.9%, respectively. Finally, we characterize the nearest-neighbor exchange couplings throughout the device and implement high-quality controlled-Z gates to generate a three-qubit Greenberger-Horne-Zeilinger (GHZ) state. These results demonstrate that spin-qubit arrays can be scaled while maintaining high-fidelity operation and establish a modular, extendable architecture for planar semiconductor quantum processors.
Silicon quantum dot spin qubits have become a promising platform for scalable quantum computing because of their small size and compatibility with industrial semiconductor manufacturing processes. Although Si/SiGe heterostructures are commonly used to host spin qubits due to their high mobility and low percolation density, the SiGe spacer creates a gap between the qubits and control electrodes, which limits the ability to tune exchange coupling. As a result, residual coupling leads to unwanted single-qubit phase shifts, making multi-qubit control more difficult. In this work, we explore swapping the roles of overlapping nanogates to overcome this issue. By reconfiguring the gate voltages, we demonstrate in situ role switching while maintaining multi-qubit control. Additionally, this method significantly improves the tunability of exchange coupling by several orders of magnitude over the traditional approach. This strategy reduces unintended single-qubit phase shifts and minimizes the complexity of multi-qubit control, supporting scalable growth with minimal experimental overhead.
Silicon-based spin qubits have emerged as a promising platform for scalable quantum computation due to their compatibility with advanced semiconductor fabrication and integration with classical CMOS electronics. As fabrication capabilities advance toward larger, higher-yield devices, the field is transitioning from academic prototypes toward processors ultimately requiring millions of qubits. This shift places increasing emphasis on developing operating techniques that scale with qubit number. In this thesis, a four qubit SiMOS processor is used to investigate three key aspects of multi-qubit operation for spin-based quantum computing. First, tuning and operation techniques for parallel double-quantum-dot unit cells are developed. Electron loading strategies enable four-qubit operation in an isolated charge configuration, and universal single- and two-qubit control is demonstrated. The native gate set is characterised using gate set tomography. The processor is operated as two unit cells that can be initialised and read out in parallel, providing two independent parity measurements per shot, without increasing operation time or degrading state preparation and measurement fidelity. Second, control techniques for generating multi-qubit entangled states and executing general quantum circuits are established. Three-qubit maximally entangled states, including cluster and Greenberger–Horne–Zeilinger states, are generated and measured with a maximum fidelity of 82.5%. A Mermin value of 3.14 is achieved, certifying genuine tripartite entanglement. A fully symmetric dynamically decoupled gate sequence is developed, extending the entanglement lifetime beyond T2* to a limit set by T2-Hahn. A workflow for compiling, executing, and analysing arbitrary circuits from OpenQASM is also demonstrated. Finally, the first mid-circuit measurements in a silicon spin-qubit system are presented. This capability is extended to feedforward control, including a novel “in-layer” method that performs conditional phase operations without routing information to the classical control layer. This approach leverages measurement-induced backaction as a control mechanism. Both in-layer and FPGA-enabled feedforward strategies are benchmarked, and their dominant error channels are identified.
Universal quantum computing promises solutions to a wide range of problems of significant scientific and socioeconomic impact that are computationally intractable using classical hardware. Since physical qubits are inherently noisy and prone to decoherence, realizing a sufficient number of logical qubits to unlock practically relevant problem classes will likely require quantum error correction, resulting in an overhead of millions of physical qubits. Among all competing hardware platforms, spin qubits in gate-defined quantum dots are uniquely positioned: single- and two-qubit gate fidelities routinely exceed the error-correction threshold, and the experimentally proven compatibility with industrial-grade semiconductor manufacturing may enable millions of qubits on a single chip. Realizing this potential, however, requires quantum processor architectures that scale to large qubit numbers with two‑dimensional connectivity while maintaining high operational fidelities. Building on the theoretical feasibility of high‑fidelity spin‑coherent electron shuttling, the SpinBus architecture is introduced to enable scaling to application-relevant qubit numbers. The SpinBus architecture leverages the conveyor-mode shuttling device named Quantum Bus (QuBus) for coherent qubit coupling over micron‑scale distances to accommodate, at the level of the quantum processor chip, wiring fan‑out and locally integrated control electronics at cryogenic temperatures. Device simulations for all relevant operations in the Si/SiGe platform validate operation fidelities exceeding 99 % as well as compatibility with the requirements of established semiconductor patterning technology. Control with room‑temperature electronics plausibly supports at least 144 qubits, while substantially larger quantum processor sizes are conceivable using cryogenic control electronics. For the experimental realization of QuBus devices, a novel high‑yield multilayer electron-beam lithography process, which can readily be adapted to different device layouts, was developed to fabricate the required > 100 aligned metallic gate electrodes. Benchmarking with a semiconductor industry‑inspired methodology and inspection of > 100 devices demonstrated 99 % gate fabrication yield and at least 5 nm overlay accuracy. Utilizing GaAs/(Al,Ga)As QuBus prototype devices with a 7 µm shuttling channel for quantized-current experiments validated key criteria for conveyor-mode shuttling, in particular linear current scaling for operation frequencies up to 40 MHz, and provided preliminary evidence consistent with quantized conveyor-mode electron transfer. These results support the viability of conveyor-mode shuttling for qubit coupling and indicate the suitability of QuBus devices for metrological applications.
Practical Quantum computing hinges on the ability to control large numbers of qubits with high fidelity. Quantum dots define a promising platform due to their compatibility with semiconductor manufacturing. Moreover, high-fidelity operations above 99.9% have been realized with individual qubits, though their performance has been limited to 98.67% when driving two qubits simultaneously. Here we present single-qubit randomized benchmarking in a two-dimensional array of spin qubits, finding native gate fidelities as high as 99.992(1)%. Furthermore, we benchmark single qubit gate performance while simultaneously driving two and four qubits, utilizing a novel benchmarking technique called N-copy randomized benchmarking, designed for simple experimental implementation and accurate simultaneous gate fidelity estimation. We find two- and four-copy randomized benchmarking fidelities of 99.905(8)% and 99.34(4)% respectively, and that next-nearest neighbor pairs are highly robust to cross-talk errors. These characterizations of single-qubit gate quality are crucial for scaling up quantum information technology.