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arXiv:2411.13955 · Quantum Science and Technology

A silicon-based ion trap chip protected from semiconductor charging

Daun Chung, Kwangyeul Choi, Woojun Lee, Chiyoon Kim, Hosung Shon, Jeonghyun Park, Beomgeun Cho, Kyungmin Lee, Suhan Kim, Seungwoo Yoo, Uihwan Jung, Changhyun Jung, Jiyong Kang, Kyunghye Kim, Roberts Berkis, Tracy E. Northup, Dong‐il Cho, Taehyun Kim

Published Apr 24, 2025• 3 citations
arXivHTMLPDF

Abstract

Abstract Silicon-based ion trap chips can benefit from existing advanced fabrication technologies, such as multi-metal layer techniques for two-dimensional architectures and silicon photonics for the integration of on-chip optical components. However, the scalability of these technologies may be compromised by semiconductor charging, where photogenerated charge carriers produce electric potentials that disrupt ion motion. Inspired by recent studies on charge distribution mechanisms in semiconductors, we developed a silicon-based chip with gold coated on all exposed silicon surfaces. This modification significantly stabilized ion motion compared to a chip without such metallic shielding, a result that underscores the detrimental effects of exposed silicon. With the mitigation of background silicon-induced fields to negligible levels, quantum operations such as sideband cooling and two-ion entangling gates, which were previously infeasible with the unshielded chip, can now be implemented.

DOI
10.1088/2058-9565/add04c

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A Silicon Surface Ion-Trap Chip with Dielectric Sidewalls Shielded by Metal Films

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An ion trap is a device to confine charged particles by utilizing electromagnetic fields.Since the trapped ions have a feasibility of the individual state manipulation, a long coherence time, and an ideal isolation from the surroundings, the ion-trap technology becomes one of the leading candidates for the physical implementation of quantum information processing.In order to build a large-scale integrated iontrap system for realizing complex quantum algorithms, microfabrication technologies have been applied to construct ion traps.The use of micro-electromechanical system (MEMS) ion-trap chip allows a scalable architecture of ion-trap arrays and integration of functional components to the trap chip, but a few side effects also arise.One of the most particular problems is stray fields generated by the charges accumulated on the sidewalls of thick dielectric pillars or the native oxide grown on metal surfaces, since the stray fields lead to ion micromotions which can cause heating and escape of the trapped ions.This dissertation presents a silicon surface ion-trap chip with dielectric sidewalls shielded by metal films.The oxide pillars supporting the top electrodes are fabricated to have overhang structures, and the upper and lower part of the pillars are coated by separate aluminum layers which are electrically isolated from each other.In order to evaluate the effects of the native ii metal oxide on the electrode surface to the charging phenomenon, a trap chip with an additional gold layer on the aluminum electrodes is also fabricated.An ultra-high vacuum (UHV) chamber, electrical connections, and an optical setup are prepared to trap 174 Yb + ions, and the ions are successfully trapped by using the experimental setup including the fabricated ion-trap chip.To evaluate the effectiveness of the proposed electrode structures, charging is intentionally induced on the chip surface by injecting a 355-nm pulse laser with 40-μW power perpendicularly to the chip surface.The intensity of the stray field is estimated by measuring the displacement of ion position after charging is induced.When the Al-based chips with exposed and Al-coated dielectric sidewalls are used, the standard deviation of the intensities of stray fields are 3.53, and 5.63 V/m, respectively.However, the standard deviation of the intensity of stray fields in the case of using Au-coated chip is 1.56 V/m, and any stray field is measured when the laser was injected on the surface or sidewalls of the gold-coated electrodes.These experimental results indicate that the gold coating on the surface of the aluminum electrodes and the sidewalls of dielectric pillars is effective for eliminating the generation of stray fields induced by static charges.

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A design is proposed for a novel ion trap quantum processor chip, microfabricated using a process based on planar silica-on-silicon techniques. The trap electrodes are of gold-coated silica and are spaced by highly doped silicon in a monolithic structure. This design allows a unit aspect-ratio trap with an ion-electrode separation below 100 μm, when using current fabrication techniques. The trapping potential is modelled and the operating parameters required to achieve motional frequencies of a few MHz are calculated. RF loss and the resultant heating of the trap chip are not found to be a factor limiting the trap's operation. This monolithic unit aspect-ratio trap is therefore expected to exhibit a deep potential well, high trap efficiency, and a low RF loss, when compared to other microfabricated traps. This technological approach is in principle scaleable to complex devices, and may form the basis for large-scale ion trap quantum processors.

New Journal of Physics•Oct 10, 2006•39 citations
Abstract Silicon-based ion trap chips can benefit from existing advanced fabrication technologies, such as multi-metal layer techniques for two-dimensional architectures and silicon photonics for the integration of on-chip optical components. However, the scalability of these technologies may be compromised by semiconductor charging, where photogenerated charge carriers produce electric potentials that disrupt ion motion. Inspired by recent studies on charge distribution mechanisms in semiconductors, we developed a silicon-based chip with gold coated on all exposed silicon surfaces. This modification significantly stabilized ion motion compared to a chip without such metallic shielding, a result that underscores the detrimental effects of exposed silicon. With the mitigation of background silicon-induced fields to negligible levels, quantum operations such as sideband cooling and two-ion entangling gates, which were previously infeasible with the unshielded chip, can now be implemented.
An ion trap is a device to confine charged particles by utilizing electromagnetic fields.Since the trapped ions have a feasibility of the individual state manipulation, a long coherence time, and an ideal isolation from the surroundings, the ion-trap technology becomes one of the leading candidates for the physical implementation of quantum information processing.In order to build a large-scale integrated iontrap system for realizing complex quantum algorithms, microfabrication technologies have been applied to construct ion traps.The use of micro-electromechanical system (MEMS) ion-trap chip allows a scalable architecture of ion-trap arrays and integration of functional components to the trap chip, but a few side effects also arise.One of the most particular problems is stray fields generated by the charges accumulated on the sidewalls of thick dielectric pillars or the native oxide grown on metal surfaces, since the stray fields lead to ion micromotions which can cause heating and escape of the trapped ions.This dissertation presents a silicon surface ion-trap chip with dielectric sidewalls shielded by metal films.The oxide pillars supporting the top electrodes are fabricated to have overhang structures, and the upper and lower part of the pillars are coated by separate aluminum layers which are electrically isolated from each other.In order to evaluate the effects of the native ii metal oxide on the electrode surface to the charging phenomenon, a trap chip with an additional gold layer on the aluminum electrodes is also fabricated.An ultra-high vacuum (UHV) chamber, electrical connections, and an optical setup are prepared to trap 174 Yb + ions, and the ions are successfully trapped by using the experimental setup including the fabricated ion-trap chip.To evaluate the effectiveness of the proposed electrode structures, charging is intentionally induced on the chip surface by injecting a 355-nm pulse laser with 40-μW power perpendicularly to the chip surface.The intensity of the stray field is estimated by measuring the displacement of ion position after charging is induced.When the Al-based chips with exposed and Al-coated dielectric sidewalls are used, the standard deviation of the intensities of stray fields are 3.53, and 5.63 V/m, respectively.However, the standard deviation of the intensity of stray fields in the case of using Au-coated chip is 1.56 V/m, and any stray field is measured when the laser was injected on the surface or sidewalls of the gold-coated electrodes.These experimental results indicate that the gold coating on the surface of the aluminum electrodes and the sidewalls of dielectric pillars is effective for eliminating the generation of stray fields induced by static charges.
Ion trap systems built upon microfabricated chips have emerged as a promising platform for quantum computing to achieve reproducible and scalable structures. However, photoinduced charging of materials in such chips can generate undesired stray electric fields that disrupt the quantum state of the ion, limiting high-fidelity quantum control essential for practical quantum computing. While crude understanding of the phenomena has been gained heuristically over the past years, explanations for the microscopic mechanism of photogenerated charge carrier dynamics remains largely elusive. Here we present a photoinduced charging model for semiconductors, whose verification is enabled by a systematic interaction between trapped ions and photoinduced stray fields from exposed silicon surfaces in our chip. We use motion-sensitive qubit transitions to directly characterize the stray field and analyze its effect on the quantum dynamics of the trapped ion. In contrast to incoherent errors arising from the thermal motion of the ion, coherent errors are induced by the stray field, whose effect is significantly imprinted during the quantum control of the ion. These errors are investigated in depth, and methods to mitigate them are discussed. Finally, we extend the implications of our study to other photoinduced charging mechanisms prevalent in ion traps and discuss considerations in fabrication to reduce semiconductor charging.
Semiconductor-based ion-trap chips are a leading platform for scalable quantum computing, but their performance is often limited by photogenerated charge carriers accumulating on exposed silicon surfaces. In this work, we present a comprehensive fabrication process for silicon-on-insulator (SOI) wafer–based ion-trap chips that addresses this challenge through optimized scallop smoothing and angled gold evaporation. We compare two scallop smoothing methods–frontside reactive ion etching (RIE) and backside RIE–and develop optimized process recipes for each using iterative test structures. Backside RIE smoothing achieves near-complete scallop removal with minimal undercut, while frontside RIE smoothing, although requiring tighter control to minimize undercut, remains viable when preservation of the buried oxide (BOX) layer is necessary. The use of SOI substrates ensures consistent device-layer thickness by leveraging the BOX as an etch-stop layer during backside deep RIE, further enhancing the reproducibility of smoothing. Finally, angled gold evaporation following the scallop smoothing process yields uniform gold coverage on vertical sidewalls without causing electrical shorts between electrode structures. Scanning electron microscopy confirms clean sidewalls and defect-free gold films. These process improvements suppress semiconductor charging, stabilize ion confinement, and enable reliable, high-fidelity quantum operations in quantum charge-coupled device architectures.
Accumulated electrostatic charges on the dielectric surfaces of ion traps are known to induce stray fields, leading to ion micromotions. In typical microfabricated ion-trap chips, metal electrodes are electrically isolated using thick dielectric pillars, which can accumulate stray charges on their sidewalls. This letter presents a new microfabrication method for ion-trap chips that reduces the exposure of dielectric surfaces to trapped ions. The dielectric pillars are fabricated with large T-shaped overhangs, and the sidewalls and top surfaces are coated with AlCu (1%) films. The bottom sides of the overhang parts provide electrical isolation. To prevent oxidation of the AlCu (1%) films, the electrode surfaces are coated with an additional Au film. The fabricated chips were implemented to trap174Yb+ions, and the laser-induced stray fields were measured. The results indicated that the trap chip fabricated by the newly developed method generates significantly smaller stray fields as compared with previous chips. [2017-0233]
Abstract A novel microfabricated ion trap chip that can geometrically minimize exposing trapped ions to stray charges on dielectric surfaces is developed. The new design utilizes a sloped loading slot to make the dielectric layers of the loading slot sidewalls invisible to the trapped ions. The designed loading slot is realized by applying silicon anisotropic etching processes, and the ion trap chip that contains the sloped loading slot is fabricated using microelectromechanical system processes. Stray charges induced by injecting an ultraviolet laser on the surface of the fabricated ion trap chip are experimentally characterized by measuring stray electric fields at the location of the trapped ions. The measured results are compared to those of a previous ion trap chip with a vertical loading slot. The magnitude of the measured stray electric field in the axial direction is within 1.5 V m−1 for the proposed ion trap chip, whereas it is approximately 10 V m−1 for the previously reported ion trap chip.
A design is proposed for a novel ion trap quantum processor chip, microfabricated using a process based on planar silica-on-silicon techniques. The trap electrodes are of gold-coated silica and are spaced by highly doped silicon in a monolithic structure. This design allows a unit aspect-ratio trap with an ion-electrode separation below 100 μm, when using current fabrication techniques. The trapping potential is modelled and the operating parameters required to achieve motional frequencies of a few MHz are calculated. RF loss and the resultant heating of the trap chip are not found to be a factor limiting the trap's operation. This monolithic unit aspect-ratio trap is therefore expected to exhibit a deep potential well, high trap efficiency, and a low RF loss, when compared to other microfabricated traps. This technological approach is in principle scaleable to complex devices, and may form the basis for large-scale ion trap quantum processors.