Semiconductor-based ion-trap chips are a leading platform for scalable quantum computing, but their performance is often limited by photogenerated charge carriers accumulating on exposed silicon surfaces. In this work, we present a comprehensive fabrication process for silicon-on-insulator (SOI) wafer–based ion-trap chips that addresses this challenge through optimized scallop smoothing and angled gold evaporation. We compare two scallop smoothing methods–frontside reactive ion etching (RIE) and backside RIE–and develop optimized process recipes for each using iterative test structures. Backside RIE smoothing achieves near-complete scallop removal with minimal undercut, while frontside RIE smoothing, although requiring tighter control to minimize undercut, remains viable when preservation of the buried oxide (BOX) layer is necessary. The use of SOI substrates ensures consistent device-layer thickness by leveraging the BOX as an etch-stop layer during backside deep RIE, further enhancing the reproducibility of smoothing. Finally, angled gold evaporation following the scallop smoothing process yields uniform gold coverage on vertical sidewalls without causing electrical shorts between electrode structures. Scanning electron microscopy confirms clean sidewalls and defect-free gold films. These process improvements suppress semiconductor charging, stabilize ion confinement, and enable reliable, high-fidelity quantum operations in quantum charge-coupled device architectures.
Semiconductor-based ion-trap chips are a leading platform for scalable quantum computing, but their performance is often limited by photogenerated charge carriers accumulating on exposed silicon surfaces. In this work, we present a comprehensive fabrication process for silicon-on-insulator (SOI) wafer–based ion-trap chips that addresses this challenge through optimized scallop smoothing and angled gold evaporation. We compare two scallop smoothing methods–frontside reactive ion etching (RIE) and backside RIE–and develop optimized process recipes for each using iterative test structures. Backside RIE smoothing achieves near-complete scallop removal with minimal undercut, while frontside RIE smoothing, although requiring tighter control to minimize undercut, remains viable when preservation of the buried oxide (BOX) layer is necessary. The use of SOI substrates ensures consistent device-layer thickness by leveraging the BOX as an etch-stop layer during backside deep RIE, further enhancing the reproducibility of smoothing. Finally, angled gold evaporation following the scallop smoothing process yields uniform gold coverage on vertical sidewalls without causing electrical shorts between electrode structures. Scanning electron microscopy confirms clean sidewalls and defect-free gold films. These process improvements suppress semiconductor charging, stabilize ion confinement, and enable reliable, high-fidelity quantum operations in quantum charge-coupled device architectures.
An ion trap is a device to confine charged particles by utilizing electromagnetic fields.Since the trapped ions have a feasibility of the individual state manipulation, a long coherence time, and an ideal isolation from the surroundings, the ion-trap technology becomes one of the leading candidates for the physical implementation of quantum information processing.In order to build a large-scale integrated iontrap system for realizing complex quantum algorithms, microfabrication technologies have been applied to construct ion traps.The use of micro-electromechanical system (MEMS) ion-trap chip allows a scalable architecture of ion-trap arrays and integration of functional components to the trap chip, but a few side effects also arise.One of the most particular problems is stray fields generated by the charges accumulated on the sidewalls of thick dielectric pillars or the native oxide grown on metal surfaces, since the stray fields lead to ion micromotions which can cause heating and escape of the trapped ions.This dissertation presents a silicon surface ion-trap chip with dielectric sidewalls shielded by metal films.The oxide pillars supporting the top electrodes are fabricated to have overhang structures, and the upper and lower part of the pillars are coated by separate aluminum layers which are electrically isolated from each other.In order to evaluate the effects of the native ii metal oxide on the electrode surface to the charging phenomenon, a trap chip with an additional gold layer on the aluminum electrodes is also fabricated.An ultra-high vacuum (UHV) chamber, electrical connections, and an optical setup are prepared to trap 174 Yb + ions, and the ions are successfully trapped by using the experimental setup including the fabricated ion-trap chip.To evaluate the effectiveness of the proposed electrode structures, charging is intentionally induced on the chip surface by injecting a 355-nm pulse laser with 40-μW power perpendicularly to the chip surface.The intensity of the stray field is estimated by measuring the displacement of ion position after charging is induced.When the Al-based chips with exposed and Al-coated dielectric sidewalls are used, the standard deviation of the intensities of stray fields are 3.53, and 5.63 V/m, respectively.However, the standard deviation of the intensity of stray fields in the case of using Au-coated chip is 1.56 V/m, and any stray field is measured when the laser was injected on the surface or sidewalls of the gold-coated electrodes.These experimental results indicate that the gold coating on the surface of the aluminum electrodes and the sidewalls of dielectric pillars is effective for eliminating the generation of stray fields induced by static charges.
Abstract Silicon-based ion trap chips can benefit from existing advanced fabrication technologies, such as multi-metal layer techniques for two-dimensional architectures and silicon photonics for the integration of on-chip optical components. However, the scalability of these technologies may be compromised by semiconductor charging, where photogenerated charge carriers produce electric potentials that disrupt ion motion. Inspired by recent studies on charge distribution mechanisms in semiconductors, we developed a silicon-based chip with gold coated on all exposed silicon surfaces. This modification significantly stabilized ion motion compared to a chip without such metallic shielding, a result that underscores the detrimental effects of exposed silicon. With the mitigation of background silicon-induced fields to negligible levels, quantum operations such as sideband cooling and two-ion entangling gates, which were previously infeasible with the unshielded chip, can now be implemented.
The surface-electrode ion trap is one of the key devices in modern ion-trapping apparatus to host the ion qubits for quantum computing. Surface traps fabricated on the silicon substrate have the versatility for complex electrode fabrication with 3-D integration capability. However, Si-induced dielectric loss has to be considered in trap design, and a ground structure is being incorporated to mitigate this concern. In this article, surface-electrode ion trap is fabricated using the standard Cu back-end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: 1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes; 2) the use of dry etching to form the fine-gap oxide trench between the electrodes for reducing the charge-induced stray electric field; 3) the use of Cu mesh ground structure to enhance the resonance performance of the trap; and 4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties are obtained from the fabricated ion trap with a leakage current failure rate of40μmare evaluated for their resonance performance with and without the ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with an output power increment of 11 and 13 dB andQfactor increment of 2 and 6 for the corresponding trap types.
Trapped ions in Paul traps (radio frequency ion traps) are a promising candidate for the realization of a quantum computer. To date, experimental demonstrations of quantum computing and information processing with trapped ions have been limited to small numbers of quantum bits (qubits). The most prominent challenge to realise ion-trap quantum computation is to scale the system and control a large number of trapped ions coherently. Surface-electrode ion trap designs which are amenable to various microfabrication techniques offer a path to achieve this. In this work, design, fabrication and key operations of two types of surface-electrode ion traps, i.e. a Y-junction trap and a two-dimensional (2D) hexagonal lattice trap developed towards scaling ion-trap architectures, are presented. The steps involved in the fabrication of the ion-trap devices included photolithography, wet etch (hydrofluoric acid etch) and dry etch (deep reactive ion and inductively coupled plasma etching), and metal evaporation. The devices were fabricated on SOI substrates with different buried oxide thicknesses (i.e. 5 µm and 10 µm) and different metals for the trap electrodes (i.e. gold and aluminium). An extremely high-breakdown voltage up to 1 kV was measured in vacuum for the SOI-built test devices with a 10 µm-thick buried oxide formed by oxide film-to-oxide film bonding process. This is attributed to the deep V-shaped undercut profile of the buried oxide layer which resulted in a large breakdown path length, and so mitigating surface breakdown effects. Owing to the V-shaped undercut profile, the surface breakdown voltage was improved by 15% for the devices fabricated on SOI substrates with a 10 µm-thick buried oxide. In the first experiment, the demonstration of ytterbium (174Yb+) ion trapping in the 2D hexagonal lattice trap is achieved with a relatively long lifetime of a laser-cooled ion up to 90 minutes and ≤ 5 minutes without cooling in ultra-high vacuum system. The 2D lattice trap design allows for reliable trapping of 2D ion lattices, rudimentary shuttling between lattice sites and deterministic introducing of defects into the ion lattice. Based on all these abilities, such a 2D lattice trap with the predicted reduction of lattice spacing down to 32 µm can be configured as a versatile architecture for 2D quantum simulations with trapped ions. In the second experiment, microparticle trapping in the 2D lattice trap, performed in air, is achieved with the longest trapping lifetime of 60 minutes. Both gold and aluminium-coated electrodes also lead to comparable trapping performances. Furthermore, the in situ levitation of microparticles is successfully demonstrated at the maximum levitation height of 30 µm. This ability provides additional control on the trapping height which increases the overall functionality of the 2D lattice trap.
In this work, we report ion trap fabrication using prevailing foundry copper back-end-of-line process on a 300mm Si platform. Surface electrodes comprising of ~3.7 µm thick Cu and ~0.2 µm thick of Au surface finish are electroplated above a ~3 µm thick of SiO2 layer on a high-resistivity Si substrate. The innovative process, which is fully compatible with CMOS back-end, enables a fine gap trench structure between the electrodes, such that the exposed dielectric area to the trapped ions is reduced. By optimizing the electroplating process, a relatively flat Cu surface is created with a thin Au layer deposited as an effective protective layer to prevent surface oxidation. The fabricated trap is wire-bonded in a CPGA package for DC and RF testing. Small size Si traps show a good RF dissipation property which is a prerequisite for ion trapping. The further integration of TSV and Si photonics shows a promising prospect in terms of electrical and optical performance enhancement of ion trap.
Through-substrate interconnects are a key technology for scaling surface-electrode ion traps (SEITs) toward large electrode counts and complex architectures. Dielectric substrates such as fused silica offer superior RF performance compared to silicon, but the reliable fabrication of void-free through-glass vias (TGVs) remains challenging. In this work, we demonstrate a SEIT fabricated on a fused silica substrate incorporating TGVs. The via-holes are formed using Selective Laser-Induced Etching and subsequently metallized with gold by electroplating. A patent-pending geometry-assisted bottom-up plating approach enables void-free filling using constant-current electroplating without electrolyte additives or pulsed deposition schemes. Electrical characterization across multiple wafers confirms a TGV-level yield above 98.8 %, demonstrating the robustness and reproducibility of the developed TGV technology. The TGVs are combined with multilayer SEIT fabrication, enabling vertical signal routing to all electrodes while maintaining an unaffected trapping surface without wire bonds. To interface the trap with external control electronics, a glass interposer providing signal fan-out to a larger pitch is designed and fabricated. The trap chip and the interposer are integrated using thermocompression bonding, forming a compact chip-to-chip assembly. The presented technology demonstrates the first fully integrated multilayer SEIT on fused silica incorporating void-free TGVs.