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A Silicon Surface Ion-Trap Chip with Dielectric Sidewalls Shielded by Metal Films

홍석준

Published Jan 1, 2017• 0 citations
OpenAlex

Abstract

An ion trap is a device to confine charged particles by utilizing electromagnetic fields.Since the trapped ions have a feasibility of the individual state manipulation, a long coherence time, and an ideal isolation from the surroundings, the ion-trap technology becomes one of the leading candidates for the physical implementation of quantum information processing.In order to build a large-scale integrated iontrap system for realizing complex quantum algorithms, microfabrication technologies have been applied to construct ion traps.The use of micro-electromechanical system (MEMS) ion-trap chip allows a scalable architecture of ion-trap arrays and integration of functional components to the trap chip, but a few side effects also arise.One of the most particular problems is stray fields generated by the charges accumulated on the sidewalls of thick dielectric pillars or the native oxide grown on metal surfaces, since the stray fields lead to ion micromotions which can cause heating and escape of the trapped ions.This dissertation presents a silicon surface ion-trap chip with dielectric sidewalls shielded by metal films.The oxide pillars supporting the top electrodes are fabricated to have overhang structures, and the upper and lower part of the pillars are coated by separate aluminum layers which are electrically isolated from each other.In order to evaluate the effects of the native ii metal oxide on the electrode surface to the charging phenomenon, a trap chip with an additional gold layer on the aluminum electrodes is also fabricated.An ultra-high vacuum (UHV) chamber, electrical connections, and an optical setup are prepared to trap 174 Yb + ions, and the ions are successfully trapped by using the experimental setup including the fabricated ion-trap chip.To evaluate the effectiveness of the proposed electrode structures, charging is intentionally induced on the chip surface by injecting a 355-nm pulse laser with 40-μW power perpendicularly to the chip surface.The intensity of the stray field is estimated by measuring the displacement of ion position after charging is induced.When the Al-based chips with exposed and Al-coated dielectric sidewalls are used, the standard deviation of the intensities of stray fields are 3.53, and 5.63 V/m, respectively.However, the standard deviation of the intensity of stray fields in the case of using Au-coated chip is 1.56 V/m, and any stray field is measured when the laser was injected on the surface or sidewalls of the gold-coated electrodes.These experimental results indicate that the gold coating on the surface of the aluminum electrodes and the sidewalls of dielectric pillars is effective for eliminating the generation of stray fields induced by static charges.

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An ion trap is a device to confine charged particles by utilizing electromagnetic fields.Since the trapped ions have a feasibility of the individual state manipulation, a long coherence time, and an ideal isolation from the surroundings, the ion-trap technology becomes one of the leading candidates for the physical implementation of quantum information processing.In order to build a large-scale integrated iontrap system for realizing complex quantum algorithms, microfabrication technologies have been applied to construct ion traps.The use of micro-electromechanical system (MEMS) ion-trap chip allows a scalable architecture of ion-trap arrays and integration of functional components to the trap chip, but a few side effects also arise.One of the most particular problems is stray fields generated by the charges accumulated on the sidewalls of thick dielectric pillars or the native oxide grown on metal surfaces, since the stray fields lead to ion micromotions which can cause heating and escape of the trapped ions.This dissertation presents a silicon surface ion-trap chip with dielectric sidewalls shielded by metal films.The oxide pillars supporting the top electrodes are fabricated to have overhang structures, and the upper and lower part of the pillars are coated by separate aluminum layers which are electrically isolated from each other.In order to evaluate the effects of the native ii metal oxide on the electrode surface to the charging phenomenon, a trap chip with an additional gold layer on the aluminum electrodes is also fabricated.An ultra-high vacuum (UHV) chamber, electrical connections, and an optical setup are prepared to trap 174 Yb + ions, and the ions are successfully trapped by using the experimental setup including the fabricated ion-trap chip.To evaluate the effectiveness of the proposed electrode structures, charging is intentionally induced on the chip surface by injecting a 355-nm pulse laser with 40-μW power perpendicularly to the chip surface.The intensity of the stray field is estimated by measuring the displacement of ion position after charging is induced.When the Al-based chips with exposed and Al-coated dielectric sidewalls are used, the standard deviation of the intensities of stray fields are 3.53, and 5.63 V/m, respectively.However, the standard deviation of the intensity of stray fields in the case of using Au-coated chip is 1.56 V/m, and any stray field is measured when the laser was injected on the surface or sidewalls of the gold-coated electrodes.These experimental results indicate that the gold coating on the surface of the aluminum electrodes and the sidewalls of dielectric pillars is effective for eliminating the generation of stray fields induced by static charges.
Accumulated electrostatic charges on the dielectric surfaces of ion traps are known to induce stray fields, leading to ion micromotions. In typical microfabricated ion-trap chips, metal electrodes are electrically isolated using thick dielectric pillars, which can accumulate stray charges on their sidewalls. This letter presents a new microfabrication method for ion-trap chips that reduces the exposure of dielectric surfaces to trapped ions. The dielectric pillars are fabricated with large T-shaped overhangs, and the sidewalls and top surfaces are coated with AlCu (1%) films. The bottom sides of the overhang parts provide electrical isolation. To prevent oxidation of the AlCu (1%) films, the electrode surfaces are coated with an additional Au film. The fabricated chips were implemented to trap174Yb+ions, and the laser-induced stray fields were measured. The results indicated that the trap chip fabricated by the newly developed method generates significantly smaller stray fields as compared with previous chips. [2017-0233]
Trapped ions within Paul traps have shown to be a promising architecture in the realisation of a quantum information processor together with the ability of providing quantum simulations. Linear Paul traps have demonstrated long coherence times with ions being well isolated from the environment, single and multi-qubit gates and the high fidelity detection of states. The scalability to large number of qubits, incorporating all the previous achievements requires an array of linear ion traps. Microfabrication techniques allow for fabrication and micron level accuracy of the trap electrode dimensions through photolithography techniques. The first part of this thesis presents the experiential setup and trapping of Yb+ ions needed to test large ion trap arrays. This include vacuum systems that can host advanced symmetric and asymmetric ion traps with up to 90 static voltage control electrodes. Demonstration of a single trapped Yb+ ion within a two-layer macroscopic ion trap is presented. with an ion-electrode distance of 310(10) µm. The anomalous heating rate and spectral noise density of the trap was measured, a main form of decoherence within ion traps. The second half of this thesis presents the design and fabrication of multi-layer asymmetric ion traps. This allows for isolated electrodes that cannot be accessed via surface pathways, allowing for higher density of electrodes as well as creating novel trap designs that allow for the potential of quantum simulations to be demonstrated. These include two-dimensional lattices and ring trap designs in which the isolated electrodes provide more control in the ion position. For the microfabrication of these traps I present a novel high-aspect ratio electroplated electrode design that provides shielding of the dielectric layer. This provides a means to mitigate stray electric field due to charge build up on the dielectric surfaces. Electrical testing of the trap structures was performed to test bulk breakdown and surface flashover of the ion trap architectures. Results showed sufficient isolation between electrodes for both radio frequency and static breakdown. Surface flashover voltage measurements over the dielectric layer showed an improvement of more than double over previous results using a new fabrication technique. This will allow for more powerful ion trap chips needed for the next generation of microfabricated ion trap arrays for scalable quantum technologies.
Abstract A novel microfabricated ion trap chip that can geometrically minimize exposing trapped ions to stray charges on dielectric surfaces is developed. The new design utilizes a sloped loading slot to make the dielectric layers of the loading slot sidewalls invisible to the trapped ions. The designed loading slot is realized by applying silicon anisotropic etching processes, and the ion trap chip that contains the sloped loading slot is fabricated using microelectromechanical system processes. Stray charges induced by injecting an ultraviolet laser on the surface of the fabricated ion trap chip are experimentally characterized by measuring stray electric fields at the location of the trapped ions. The measured results are compared to those of a previous ion trap chip with a vertical loading slot. The magnitude of the measured stray electric field in the axial direction is within 1.5 V m−1 for the proposed ion trap chip, whereas it is approximately 10 V m−1 for the previously reported ion trap chip.
Abstract Silicon-based ion trap chips can benefit from existing advanced fabrication technologies, such as multi-metal layer techniques for two-dimensional architectures and silicon photonics for the integration of on-chip optical components. However, the scalability of these technologies may be compromised by semiconductor charging, where photogenerated charge carriers produce electric potentials that disrupt ion motion. Inspired by recent studies on charge distribution mechanisms in semiconductors, we developed a silicon-based chip with gold coated on all exposed silicon surfaces. This modification significantly stabilized ion motion compared to a chip without such metallic shielding, a result that underscores the detrimental effects of exposed silicon. With the mitigation of background silicon-induced fields to negligible levels, quantum operations such as sideband cooling and two-ion entangling gates, which were previously infeasible with the unshielded chip, can now be implemented.
Ions trapped in a quadrupole Paul trap have been considered one of the strong physical candidates to implement quantum information processing. This is due to their long coherence time and their capability to manipulate and detect individual quantum bits (qubits). In more recent years, microfabricated surface ion traps have received more attention for large-scale integrated qubit platforms. This paper presents a microfabrication methodology for ion traps using micro-electro-mechanical system (MEMS) technology, including the fabrication method for a 14 µm-thick dielectric layer and metal overhang structures atop the dielectric layer. In addition, an experimental procedure for trapping ytterbium (Yb) ions of isotope 174 (174Yb+) using 369.5 nm, 399 nm, and 935 nm diode lasers is described. These methodologies and procedures involve many scientific and engineering disciplines, and this paper first presents the detailed experimental procedures. The methods discussed in this paper can easily be extended to the trapping of Yb ions of isotope 171 (171Yb+) and to the manipulation of qubits.
Ions trapped in a quadrupole Paul trap have been considered one of the strong physical candidates to implement quantum information processing. This is due to their long coherence time and their capability to manipulate and detect individual quantum bits (qubits). In more recent years, microfabricated surface ion traps have received more attention for large-scale integrated qubit platforms. This paper presents a microfabrication methodology for ion traps using micro-electro-mechanical system (MEMS) technology, including the fabrication method for a 14 µm-thick dielectric layer and metal overhang structures atop the dielectric layer. In addition, an experimental procedure for trapping ytterbium (Yb) ions of isotope 174 (174Yb+) using 369.5 nm, 399 nm, and 935 nm diode lasers is described. These methodologies and procedures involve many scientific and engineering disciplines, and this paper first presents the detailed experimental procedures. The methods discussed in this paper can easily be extended to the trapping of Yb ions of isotope 171 (171Yb+) and to the manipulation of qubits.