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Quantum Science and Technology

A microfabricated ion trap chip with a sloped loading slot to minimize exposing trapped ions to stray charges

Changhyun Jung, Woojun Lee, Junho Jeong, Minjae Lee, Yunjae Park, Taehyun Kim, Dong‐il Cho

Published Jul 1, 2021• 10 citations
Publisher

Abstract

Abstract A novel microfabricated ion trap chip that can geometrically minimize exposing trapped ions to stray charges on dielectric surfaces is developed. The new design utilizes a sloped loading slot to make the dielectric layers of the loading slot sidewalls invisible to the trapped ions. The designed loading slot is realized by applying silicon anisotropic etching processes, and the ion trap chip that contains the sloped loading slot is fabricated using microelectromechanical system processes. Stray charges induced by injecting an ultraviolet laser on the surface of the fabricated ion trap chip are experimentally characterized by measuring stray electric fields at the location of the trapped ions. The measured results are compared to those of a previous ion trap chip with a vertical loading slot. The magnitude of the measured stray electric field in the axial direction is within 1.5 V m−1 for the proposed ion trap chip, whereas it is approximately 10 V m−1 for the previously reported ion trap chip.

DOI
10.1088/2058-9565/ac107d

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Abstract A novel microfabricated ion trap chip that can geometrically minimize exposing trapped ions to stray charges on dielectric surfaces is developed. The new design utilizes a sloped loading slot to make the dielectric layers of the loading slot sidewalls invisible to the trapped ions. The designed loading slot is realized by applying silicon anisotropic etching processes, and the ion trap chip that contains the sloped loading slot is fabricated using microelectromechanical system processes. Stray charges induced by injecting an ultraviolet laser on the surface of the fabricated ion trap chip are experimentally characterized by measuring stray electric fields at the location of the trapped ions. The measured results are compared to those of a previous ion trap chip with a vertical loading slot. The magnitude of the measured stray electric field in the axial direction is within 1.5 V m−1 for the proposed ion trap chip, whereas it is approximately 10 V m−1 for the previously reported ion trap chip.
Accumulated electrostatic charges on the dielectric surfaces of ion traps are known to induce stray fields, leading to ion micromotions. In typical microfabricated ion-trap chips, metal electrodes are electrically isolated using thick dielectric pillars, which can accumulate stray charges on their sidewalls. This letter presents a new microfabrication method for ion-trap chips that reduces the exposure of dielectric surfaces to trapped ions. The dielectric pillars are fabricated with large T-shaped overhangs, and the sidewalls and top surfaces are coated with AlCu (1%) films. The bottom sides of the overhang parts provide electrical isolation. To prevent oxidation of the AlCu (1%) films, the electrode surfaces are coated with an additional Au film. The fabricated chips were implemented to trap174Yb+ions, and the laser-induced stray fields were measured. The results indicated that the trap chip fabricated by the newly developed method generates significantly smaller stray fields as compared with previous chips. [2017-0233]
An ion trap is a device to confine charged particles by utilizing electromagnetic fields.Since the trapped ions have a feasibility of the individual state manipulation, a long coherence time, and an ideal isolation from the surroundings, the ion-trap technology becomes one of the leading candidates for the physical implementation of quantum information processing.In order to build a large-scale integrated iontrap system for realizing complex quantum algorithms, microfabrication technologies have been applied to construct ion traps.The use of micro-electromechanical system (MEMS) ion-trap chip allows a scalable architecture of ion-trap arrays and integration of functional components to the trap chip, but a few side effects also arise.One of the most particular problems is stray fields generated by the charges accumulated on the sidewalls of thick dielectric pillars or the native oxide grown on metal surfaces, since the stray fields lead to ion micromotions which can cause heating and escape of the trapped ions.This dissertation presents a silicon surface ion-trap chip with dielectric sidewalls shielded by metal films.The oxide pillars supporting the top electrodes are fabricated to have overhang structures, and the upper and lower part of the pillars are coated by separate aluminum layers which are electrically isolated from each other.In order to evaluate the effects of the native ii metal oxide on the electrode surface to the charging phenomenon, a trap chip with an additional gold layer on the aluminum electrodes is also fabricated.An ultra-high vacuum (UHV) chamber, electrical connections, and an optical setup are prepared to trap 174 Yb + ions, and the ions are successfully trapped by using the experimental setup including the fabricated ion-trap chip.To evaluate the effectiveness of the proposed electrode structures, charging is intentionally induced on the chip surface by injecting a 355-nm pulse laser with 40-μW power perpendicularly to the chip surface.The intensity of the stray field is estimated by measuring the displacement of ion position after charging is induced.When the Al-based chips with exposed and Al-coated dielectric sidewalls are used, the standard deviation of the intensities of stray fields are 3.53, and 5.63 V/m, respectively.However, the standard deviation of the intensity of stray fields in the case of using Au-coated chip is 1.56 V/m, and any stray field is measured when the laser was injected on the surface or sidewalls of the gold-coated electrodes.These experimental results indicate that the gold coating on the surface of the aluminum electrodes and the sidewalls of dielectric pillars is effective for eliminating the generation of stray fields induced by static charges.
The stray charges induced on ion trap surfaces can push trapped ions away from a pseudopotential null point. This can cause the micromotion of the trapped ions that in turn results in ion heating. One of the causes of stray charges is laser scattering on dielectric surfaces. The amount of laser-induced stray charges can be related to the area of the dielectric surface exposed to the ions. In this paper, stray charges are intentionally created at various dielectric surfaces on a microfabricated ion trap chip using a laser, and the resulting ion motion is measured. The ion movements are estimated by comparing ion positions before and after laser irradiation. When the laser irradiates a dielectric surface with an area of approximately 1,750 μm2exposed to the ion, the ion moves approximately −4.8 μm in the axial direction. When the laser irradiates another dielectric surface with an area of approximately 140 μm2exposed to the ion, the ion moves approximately −0.6 μm. The ratio between the ion movements corresponds to the ratio between the areas of each dielectric surface directly exposed to the ion normalized to the distance between the ion and the laser-induced stray charges. The results indicate the importance of reducing the area of dielectric surfaces that are directly in the line of laser paths.
We describe a novel monolithic ion trap that combines the flexibility and scalability of silicon microfabrication technologies with the superior trapping characteristics of traditional four-rod Paul traps. The performace of the proposed microfabricated trap approaches that of the macroscopic structures. The fabrication process creates an angled through-chip slot which allows backside ion loading and through-laser access while avoiding surface light scattering and dielectric charging. The trap geometry and dimensions are optimized for confining long ion chains with equal ion spacing [G.-D. Lin, et al., Europhys. Lett. 86, 60004 (2009)]. Control potentials have been derived to produce linear, equally spaced ion chains of up to 50 ions spaced at 10 um. With the deep trapping depths achievable in this design, we expect that these chains will be sufficiently long-lived to be used in quantum simulations of magnetic systems [E.E. Edwards, et al., Phys. Rev. B 82, 060412(R) (2010)]. The trap is currently being fabricated at Georgia Tech using VLSI techniques.
This paper presents a new microfabrication method for surface ion traps and experimental results with trapped ions. Fabricating ion trap chips is a very formidable task because the top electrodes are vertically spaced more than 10 µm from the bottom electrodes with an indented dielectric layer in the middle. Previous ion traps were fabricated using TEOS timed etch or tungsten sacrificial etch techniques. This paper presents a new microfabrication method, using copper as a sacrificial material for an aluminum-oxide-aluminum ion trap structure. Using the developed method the overhang dimensions of the top aluminum electrodes can be accurately controlled. Fabricated ion trap chips are installed in a 1 × 10−11Torr vacuum environment for ion trapping experiments. Successful results in trapping strings of171Yb+and174Yb+ions as well as manipulating171Yb+ions for qubit operation are demonstrated.
The surface-electrode ion trap is one of the key devices in modern ion-trapping apparatus to host the ion qubits for quantum computing. Surface traps fabricated on the silicon substrate have the versatility for complex electrode fabrication with 3-D integration capability. However, Si-induced dielectric loss has to be considered in trap design, and a ground structure is being incorporated to mitigate this concern. In this article, surface-electrode ion trap is fabricated using the standard Cu back-end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: 1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes; 2) the use of dry etching to form the fine-gap oxide trench between the electrodes for reducing the charge-induced stray electric field; 3) the use of Cu mesh ground structure to enhance the resonance performance of the trap; and 4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties are obtained from the fabricated ion trap with a leakage current failure rate of40 μm40~\mu \text{m}40 μmare evaluated for their resonance performance with and without the ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with an output power increment of 11 and 13 dB andQQQfactor increment of 2 and 6 for the corresponding trap types.