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arXiv:1712.05561 · IEEE International Superconductive Electronics Conference (ISEC)

Design of Quantum Annealing Machine for Prime Factoring

Masaaki Maezawa, Kentaro Imafuku, Mutsuo Hidaka, H. Koike, Shiro Kawabata

Published Jun 1, 2017• 14 citations
arXivHTMLPDF

Abstract

We propose a prime factoring machine operated in a frame work of quantum annealing (QA). The idea is inverse operation of a quantum-mechanically reversible multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The circuits are to be implemented and fabricated by using superconducting integrated circuit technology. We propose a three-dimensional packaging scheme of a qubit-chip / interposer / package-substrate structure for realizing practically-large scale QA systems.

DOI
10.1109/isec.2017.8314195

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We propose a prime factoring machine operated in a frame work of quantum annealing (QA). The idea is inverse operation of a quantum-mechanically reversible multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The circuits are to be implemented and fabricated by using superconducting integrated circuit technology. We propose a three-dimensional packaging scheme of a qubit-chip / interposer / package-substrate structure for realizing practically-large scale QA systems.
We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is inverse operation of a multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The invertible operation of QA logic gates consisting of superconducting flux qubits was confirmed by circuit simulation with classical noise sources. The circuits were implemented and fabricated by using superconducting integrated circuit technologies with Nb/AlOx/Nb Josephson junctions. We also propose a 2.5Dimensional packaging scheme of a qubit-chip/interpose /package-substrate structure for realizing practically large-scale QA systems.
Prime factorization (P = M × N) is a promising application for quantum computing. Shor's algorithm is a key concept for breaking the limit for analyzing P, which cannot be effectively solved by classical computation; however, the algorithm requires error-correctable logical qubits. Here, we describe a quantum annealing method for solving prime factorization. A superconducting quantum circuit with native implementation of the multiplier Hamiltonian provides combinations of M and N as a solution for number P after annealing. This circuit is robust and can be expanded easily to scale up the analysis. We present an experimental and theoretical exploration of the multiplier unit. We demonstrate the 2-bit factorization in a circuit simulation and experimentally at 10 mK. We also explain how the current conditions can be used to obtain high success probability and all candidate factorized elements.
Prime factorization (P=M×N) is considered to be a promising application in quantum computations. We perform 4-bit factorization in experiments using a superconducting flux qubit toward quantum annealing (QA). Our proposed method uses a superconducting quantum circuit implementing a multiplier Hamiltonian, which provides combinations ofMandNas a factorization solution after QA when the integerPis initially set. The circuit comprises multiple multiplier units (MUs) combined with connection qubits. The key points are a native implementation of the multiplier Hamiltonian to the superconducting quantum circuit and its fabrication using a Nb multilayer process with a Josephson junction dedicated to the qubit. The 4-bit factorization circuit comprises 32 superconducting flux qubits. Our method has superior scalability because the Hamiltonian is implemented with fewer qubits than in conventional methods using a chimera graph architecture. We perform experiments at 10 mK to clarify the validity of interconnections of a MU using qubits. We demonstrate experiments at 4.2 K and simulations for the factorization of integers four, six, and nine.
This paper investigates novel techniques to solve prime factorization by quantum annealing (QA). First, we present a very-compact modular encoding of a multiplier circuit into the architecture of current D-Wave QA devices. The key contribution is a compact encoding of a controlled full-adder into an 8-qubit module in the Pegasus topology, which we synthesized using Optimization Modulo Theories. This allows us to encode up to a 21 × 12-bit multiplier (and a 22 × 8-bit one) into the Pegasus 5760-qubit topology of current annealers. To the best of our knowledge, these are the largest factorization problems ever encoded into a quantum annealer. Second, we investigated the problem of actually solving encoded PF problems by running an extensive experimental evaluation on a D-Wave Advantage 4.1 quantum annealer. In the experiments we introduced different approaches to initialize the multiplier qubits and adopted several performance enhancement techniques. Overall, 8,219,999 = 32,749 × 251 was the highest prime product we were able to factorize within the limits of our QPU resources. To the best of our knowledge, this is the largest number which was ever factorized by means of a quantum annealer; also, this is the largest number which was ever factorized by means of any quantum device without relying on external search or preprocessing procedures run on classical computers.
Abstract Probabilistic computing has been introduced to operate functional networks using a probabilistic bit (p-bit), broadening the computational abilities in non-deterministic polynomial searching operations. However, previous developments have focused on emulating the operation of quantum computers similarly, implementing every p-bit with large weight-sum matrix multiplication blocks and requiring tens of times more p-bits than semiprime bits. In addition, operations based on a conventional simulated annealing scheme required a large number of sampling operations, which deteriorated the performance of the Ising machines. Here we introduce a prime factorization machine with a virtually connected Boltzmann machine and probabilistic annealing method, which are designed to reduce the hardware complexity and number of sampling operations. From 10-bit to 64-bit prime factorizations were performed, and the machine offers up to 1.2 × 108 times improvement in the number of sampling operations compared with previous factorization machines, with a 22-fold smaller hardware resource.
Experimental demonstrations of quantum annealing with “native” implementation of Boolean logic Hamiltonians are reported. As a superconducting integrated circuit, a problem Hamiltonian whose set of ground states is consistent with a given truth table is implemented for quantum annealing with no redundant qubits. As examples of the truth table,nandandnorare successfully fabricated as an identical circuit. Similarly, a native implementation of a multiplier comprising six superconducting flux qubits is also demonstrated. These native implementations of Hamiltonians consistent with Boolean logic provide an efficient and scalable way of applying annealing computation to so-called circuit satisfiability problems that aim to find a set of inputs consistent with a given output over any Boolean logic functions, especially those like factorization through a multiplier Hamiltonian. A proof-of-concept demonstration of a hybrid computing architecture for domain-specific quantum computing is described.