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Scientific Reports

A quantum-inspired probabilistic prime factorization based on virtually connected Boltzmann machine and probabilistic annealing

Hyundo Jung, Hyunjin Kim, Woojin Lee, Jinwoo Jeon, Yohan Choi, Taehyeong Park, Chulwoo Kim

Published Sep 27, 2023• 5 citations
Publisher

Abstract

Abstract Probabilistic computing has been introduced to operate functional networks using a probabilistic bit (p-bit), broadening the computational abilities in non-deterministic polynomial searching operations. However, previous developments have focused on emulating the operation of quantum computers similarly, implementing every p-bit with large weight-sum matrix multiplication blocks and requiring tens of times more p-bits than semiprime bits. In addition, operations based on a conventional simulated annealing scheme required a large number of sampling operations, which deteriorated the performance of the Ising machines. Here we introduce a prime factorization machine with a virtually connected Boltzmann machine and probabilistic annealing method, which are designed to reduce the hardware complexity and number of sampling operations. From 10-bit to 64-bit prime factorizations were performed, and the machine offers up to 1.2 × 108 times improvement in the number of sampling operations compared with previous factorization machines, with a 22-fold smaller hardware resource.

DOI
10.1038/s41598-023-43054-5

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Abstract Probabilistic computing has been introduced to operate functional networks using a probabilistic bit (p-bit), broadening the computational abilities in non-deterministic polynomial searching operations. However, previous developments have focused on emulating the operation of quantum computers similarly, implementing every p-bit with large weight-sum matrix multiplication blocks and requiring tens of times more p-bits than semiprime bits. In addition, operations based on a conventional simulated annealing scheme required a large number of sampling operations, which deteriorated the performance of the Ising machines. Here we introduce a prime factorization machine with a virtually connected Boltzmann machine and probabilistic annealing method, which are designed to reduce the hardware complexity and number of sampling operations. From 10-bit to 64-bit prime factorizations were performed, and the machine offers up to 1.2 × 108 times improvement in the number of sampling operations compared with previous factorization machines, with a 22-fold smaller hardware resource.
Probabilistic computing has been introduced to operate functional networks using a probabilistic bit (p-bit), generating 0 or 1 probabilistically from its electrical input. In contrast to quantum computers, probabilistic computing enables the operation of adiabatic algorithms even at room temperature, and is expected to broaden computational abilities in non-deterministic polynomial searching and learning problems. However, previous developments of probabilistic machines have focused on emulating the operation of quantum computers similarly, implementing every p-bit with large weight-sum matrix multiplication blocks or requiring tens of times more p-bits than semiprime bits. Furthermore, previous probabilistic machines adopted the graph model of quantum computers for updating the hardware connections, which further increased the number of sampling operations. Here we introduce a digitally accelerated prime factorization machine with a virtually connected Boltzmann machine and probabilistic annealing method, designed to reduce the complexity and number of sampling operations to below those of previous probabilistic factorization machines. In 10-bit to 64-bit factorizations were performed to assess the effectiveness of the machine, and the machine offers 1.2 X 10^8 times improvement in the number of sampling operations compared with previous factorization machines, with a 22-fold smaller hardware resource. This work shows that probabilistic machines can be implemented in a cost-effective manner using a field-programmable gate array, and hence we suggest that probabilistic computers can be employed for solving various large NP searching problems in the near future.
Factorization of a large semiprime is a hard problem on classical computers, and quantum annealing is one way to solve the prime factorization problem by converting to a combinatorial optimization problem. A conversion method using the block-wise sum of partial products has been proposed but that works well up to numbers with 21-bit. To enhance the input bit width of the prime factorization, the paper introduces three proposals for prime factorization based on quantum annealing. First one is to divide the original problem into several sub-problems and solve them using multiple annealings. Second and third ones are analytical variable reduction of LSB and MSB parts. The proposals have been implemented on Python for Fixstars Amplify Annealing Engine (AE) and can factorize numbers with 46-bit or less. The proposals can also factorize numbers up to 57-bit but with a lot of trials for each number.
We propose a prime factoring machine operated in a frame work of quantum annealing (QA). The idea is inverse operation of a quantum-mechanically reversible multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The circuits are to be implemented and fabricated by using superconducting integrated circuit technology. We propose a three-dimensional packaging scheme of a qubit-chip / interposer / package-substrate structure for realizing practically-large scale QA systems.
Neural quantum states efficiently represent many-body wavefunctions with neural networks, but the cost of Monte Carlo sampling limits their scaling to large system sizes. Here we address this challenge by combining sparse Boltzmann machine architectures with probabilistic computing hardware. We implement a probabilistic computer on field-programmable gate arrays (FPGAs) and use it as a fast sampler for energy-based neural quantum states. For the two-dimensional transverse-field Ising model at criticality, we obtain accurate ground-state energies for lattices up to 80$\times$80 (6400 spins) using a custom multi-FPGA cluster. Furthermore, we introduce a dual-sampling algorithm to train deep Boltzmann machines, replacing intractable marginalization with conditional sampling over auxiliary layers. This enables the training of sparse deep models and improves parameter efficiency relative to shallow networks. We further implement this algorithm on a single FPGA, demonstrating the training of deep Boltzmann machines for systems as large as 30×3030 \times 3030×30 (900 spins). Together, these results demonstrate that probabilistic hardware can overcome the sampling bottleneck in variational simulation of quantum many-body systems, opening a path to larger system sizes and deeper variational architectures.
Digital computing is based on the notion of deterministic bits that are 0 or 1. At the other extreme, quantum computing is based on q-bits that are delicate, coherent superpositions of 0 and 1. In this paper, we describe an intermediate approach between these two extremes, namely Probabilistic Computing, based on the notion of probabilistic or p-bits that fluctuate between 0 and 1. Hardware p-bits can be compactly realized from emerging spintronic building blocks that are smaller, more energy efficient compared to their traditional CMOS implementations. Probabilistic circuits built out of interconnected p-bits can be useful for a host of quantum computing inspired algorithms.
Factorization of large semiprimes remains one of the most challenging problems for classical computers. Shor’s algorithm offers a quantum approach that reduces computational complexity, but its practical application is currently limited by hardware constraints. Meanwhile, as a provisional approach, quantum annealing (QA) has been explored through formulations of the quadratic unconstrained binary optimization (QUBO) problem. Among existing methods, the blockwise partial-product approach effectively reduced the QUBO variable count but was limited to semiprimes up to 21 bits. To extend factorization to larger semiprimes, this paper addresses key engineering challenges in constructing efficient QUBO formulations for prime factorization. We propose five techniques to reduce variable counts and improve scalability with current QA hardware: (1) dividing the problem into subproblems with partial constraints; (2) applying analytical reductions near the LSB; (3) applying analytical reductions near the MSB; (4) exploiting special patterns in semiprimes, with odd bit widths and long MSB-side zero sequences; and (5) balancing variable usage across both sides of the subproblem. Integrated into a QUBO converter, these methods enable stable factorization of semiprimes up to 47-bits within 20 seconds and can extend to special 2049-bit instances with 1001 consecutive MSB-side zeros.