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arXiv:2106.08681 · IEEE Transactions on Quantum Engineering

Experimental Demonstrations of Native Implementation of Boolean Logic Hamiltonian in a Superconducting Quantum Annealer

Daisuke Saida, Yuki Yamanashi, Mutsuo Hidaka, Fuminori Hirayama, Kentaro Imafuku, Shuichi Nagasawa, Shiro Kawabata

Published Jan 1, 2021• 8 citations
arXivHTMLPDF

Abstract

Experimental demonstrations of quantum annealing with “native” implementation of Boolean logic Hamiltonians are reported. As a superconducting integrated circuit, a problem Hamiltonian whose set of ground states is consistent with a given truth table is implemented for quantum annealing with no redundant qubits. As examples of the truth table,nandandnorare successfully fabricated as an identical circuit. Similarly, a native implementation of a multiplier comprising six superconducting flux qubits is also demonstrated. These native implementations of Hamiltonians consistent with Boolean logic provide an efficient and scalable way of applying annealing computation to so-called circuit satisfiability problems that aim to find a set of inputs consistent with a given output over any Boolean logic functions, especially those like factorization through a multiplier Hamiltonian. A proof-of-concept demonstration of a hybrid computing architecture for domain-specific quantum computing is described.

DOI
10.1109/tqe.2021.3106776

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Experimental demonstrations of quantum annealing with “native” implementation of Boolean logic Hamiltonians are reported. As a superconducting integrated circuit, a problem Hamiltonian whose set of ground states is consistent with a given truth table is implemented for quantum annealing with no redundant qubits. As examples of the truth table,nandandnorare successfully fabricated as an identical circuit. Similarly, a native implementation of a multiplier comprising six superconducting flux qubits is also demonstrated. These native implementations of Hamiltonians consistent with Boolean logic provide an efficient and scalable way of applying annealing computation to so-called circuit satisfiability problems that aim to find a set of inputs consistent with a given output over any Boolean logic functions, especially those like factorization through a multiplier Hamiltonian. A proof-of-concept demonstration of a hybrid computing architecture for domain-specific quantum computing is described.
The applicability of quantum annealing to various problems can be improved by expressing the Hamiltonian using a circuit satisfiability problem. We investigate the detailed characteristics of the NOR/NAND functions of a superconducting quantum circuit, which are the basic building blocks to implementing various types of problem Hamiltonians. The circuit is composed of superconducting flux qubits with all-to-all connectivity, where direct magnetic couplers are utilized instead of the variable couplers in the conventional superconducting quantum circuit. This configuration provides efficient scalability because the problem Hamiltonian is implemented using fewer qubits. We present an experiment with a complete logic operation of NOR/NAND, in which the circuit produces results with a high probability of success for arbitrary combinations of inputs. The features of the quantum circuit agree qualitatively with the theory, especially the mechanism for an operation under external flux modulation. Moreover, by calibrating the bias conditions to compensate for the offset flux from the surrounding circuit, the quantum circuit quantitatively agrees with the theory. To achieve true quantum annealing, we discuss the effects of the reduction in electric noise in quantum annealing.
Prime factorization (P = M × N) is a promising application for quantum computing. Shor's algorithm is a key concept for breaking the limit for analyzing P, which cannot be effectively solved by classical computation; however, the algorithm requires error-correctable logical qubits. Here, we describe a quantum annealing method for solving prime factorization. A superconducting quantum circuit with native implementation of the multiplier Hamiltonian provides combinations of M and N as a solution for number P after annealing. This circuit is robust and can be expanded easily to scale up the analysis. We present an experimental and theoretical exploration of the multiplier unit. We demonstrate the 2-bit factorization in a circuit simulation and experimentally at 10 mK. We also explain how the current conditions can be used to obtain high success probability and all candidate factorized elements.
Prime factorization (P=M×N) is considered to be a promising application in quantum computations. We perform 4-bit factorization in experiments using a superconducting flux qubit toward quantum annealing (QA). Our proposed method uses a superconducting quantum circuit implementing a multiplier Hamiltonian, which provides combinations ofMandNas a factorization solution after QA when the integerPis initially set. The circuit comprises multiple multiplier units (MUs) combined with connection qubits. The key points are a native implementation of the multiplier Hamiltonian to the superconducting quantum circuit and its fabrication using a Nb multilayer process with a Josephson junction dedicated to the qubit. The 4-bit factorization circuit comprises 32 superconducting flux qubits. Our method has superior scalability because the Hamiltonian is implemented with fewer qubits than in conventional methods using a chimera graph architecture. We perform experiments at 10 mK to clarify the validity of interconnections of a MU using qubits. We demonstrate experiments at 4.2 K and simulations for the factorization of integers four, six, and nine.
The Boolean satisfiability problem (SAT) is widely applied in modern tasks of microelectronics design automation. An important application of such a task is the design of logic circuits with specified characteristics from a given set of logic gates. To solve an SAT problem, both standard solvers and modern optimization tools can be used, including a relatively new hardware tool for solving the quantum annealing problem. The solution of this problem can be performed on a quantum annealing system by constructing a socalled Boolean network according to special rules and selecting an appropriate objective function. The article discusses the practical application of quantum annealing to the construction of short logic circuits by solving an SAT problem based on the methods proposed in the literature, and also analyzes the practical aspects of applying such methods to the construction of quantum circuits.
We propose a prime factoring machine operated in a frame work of quantum annealing (QA). The idea is inverse operation of a quantum-mechanically reversible multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The circuits are to be implemented and fabricated by using superconducting integrated circuit technology. We propose a three-dimensional packaging scheme of a qubit-chip / interposer / package-substrate structure for realizing practically-large scale QA systems.
We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is inverse operation of a multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The invertible operation of QA logic gates consisting of superconducting flux qubits was confirmed by circuit simulation with classical noise sources. The circuits were implemented and fabricated by using superconducting integrated circuit technologies with Nb/AlOx/Nb Josephson junctions. We also propose a 2.5Dimensional packaging scheme of a qubit-chip/interpose /package-substrate structure for realizing practically large-scale QA systems.