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arXiv:1809.01425 · Journal of the Physical Society of Japan

Toward Practical-Scale Quantum Annealing Machine for Prime Factoring

Masaaki Maezawa, Go Fujii, Mutsuo Hidaka, Kentaro Imafuku, Katsuya Kikuchi, Hanpei Koike, Kazumasa Makise, Shuichi Nagasawa, Hiroshi Nakagawa, Masahiro Ukibe, Shiro Kawabata

Published Apr 11, 2019• 46 citations
arXivHTMLPDF

Abstract

We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is inverse operation of a multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The invertible operation of QA logic gates consisting of superconducting flux qubits was confirmed by circuit simulation with classical noise sources. The circuits were implemented and fabricated by using superconducting integrated circuit technologies with Nb/AlOx/Nb Josephson junctions. We also propose a 2.5Dimensional packaging scheme of a qubit-chip/interpose /package-substrate structure for realizing practically large-scale QA systems.

DOI
10.7566/jpsj.88.061012

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We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is inverse operation of a multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The invertible operation of QA logic gates consisting of superconducting flux qubits was confirmed by circuit simulation with classical noise sources. The circuits were implemented and fabricated by using superconducting integrated circuit technologies with Nb/AlOx/Nb Josephson junctions. We also propose a 2.5Dimensional packaging scheme of a qubit-chip/interpose /package-substrate structure for realizing practically large-scale QA systems.
We propose a prime factoring machine operated in a frame work of quantum annealing (QA). The idea is inverse operation of a quantum-mechanically reversible multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The circuits are to be implemented and fabricated by using superconducting integrated circuit technology. We propose a three-dimensional packaging scheme of a qubit-chip / interposer / package-substrate structure for realizing practically-large scale QA systems.
Prime factorization (P=M×N) is considered to be a promising application in quantum computations. We perform 4-bit factorization in experiments using a superconducting flux qubit toward quantum annealing (QA). Our proposed method uses a superconducting quantum circuit implementing a multiplier Hamiltonian, which provides combinations ofMandNas a factorization solution after QA when the integerPis initially set. The circuit comprises multiple multiplier units (MUs) combined with connection qubits. The key points are a native implementation of the multiplier Hamiltonian to the superconducting quantum circuit and its fabrication using a Nb multilayer process with a Josephson junction dedicated to the qubit. The 4-bit factorization circuit comprises 32 superconducting flux qubits. Our method has superior scalability because the Hamiltonian is implemented with fewer qubits than in conventional methods using a chimera graph architecture. We perform experiments at 10 mK to clarify the validity of interconnections of a MU using qubits. We demonstrate experiments at 4.2 K and simulations for the factorization of integers four, six, and nine.
Prime factorization (P = M × N) is a promising application for quantum computing. Shor's algorithm is a key concept for breaking the limit for analyzing P, which cannot be effectively solved by classical computation; however, the algorithm requires error-correctable logical qubits. Here, we describe a quantum annealing method for solving prime factorization. A superconducting quantum circuit with native implementation of the multiplier Hamiltonian provides combinations of M and N as a solution for number P after annealing. This circuit is robust and can be expanded easily to scale up the analysis. We present an experimental and theoretical exploration of the multiplier unit. We demonstrate the 2-bit factorization in a circuit simulation and experimentally at 10 mK. We also explain how the current conditions can be used to obtain high success probability and all candidate factorized elements.
Experimental demonstrations of quantum annealing with “native” implementation of Boolean logic Hamiltonians are reported. As a superconducting integrated circuit, a problem Hamiltonian whose set of ground states is consistent with a given truth table is implemented for quantum annealing with no redundant qubits. As examples of the truth table,nandandnorare successfully fabricated as an identical circuit. Similarly, a native implementation of a multiplier comprising six superconducting flux qubits is also demonstrated. These native implementations of Hamiltonians consistent with Boolean logic provide an efficient and scalable way of applying annealing computation to so-called circuit satisfiability problems that aim to find a set of inputs consistent with a given output over any Boolean logic functions, especially those like factorization through a multiplier Hamiltonian. A proof-of-concept demonstration of a hybrid computing architecture for domain-specific quantum computing is described.
This chapter focuses on the application of Nb Josephson junctions (JJs) in quantum annealing (QA). It begins with a brief introduction to diffident strategies for implementing quantum computation (QC) with an emphasis on quantum annealing. The chapter presents the basic physics of the simplest superconducting flux qubit: radio frequency superconducting quantum interference devices (RF-SQUID). It gives a brief description on the design and realization of couplers, and control and measurement circuitry using Nb Josephson junctions. The chapter describes a scalable architecture upon which quantum annealing processors consisting up to 1024 superconducting flux qubits made of more than 104 Nb Josephson junctions. It discusses evidence on whether D-Wave 2X, which is the latest quantum annealing processor available, works as expected. The chapter also focuses on the physics and application of RF-SQUID flux qubits because the fundamental building blocks of the most advanced quantum annealers demonstrated so far are variations of superconducting flux qubits with one Josephson junction, a.k.a. the RF-SQUID.
We have developed a quantum annealing processor, based on an array of tunable coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process. Implementing this type of processor at a scale of 512 qubits and 1472 programmable interqubit couplers and operating at ~ 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here, we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular, we will review some of the design tradeoffs at play in the floor planning of the physical layout, driven by the desire to have an algorithmically useful set of interqubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context, we have developed a new ultralow-power embedded superconducting digital-to-analog flux converter (DAC) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is ~ 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see, for example, the recent reporting by Jones).