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arXiv:1605.08009 · IEEE Transactions on Applied Superconductivity

Investigating Surface Loss Effects in Superconducting Transmon Qubits

Jay M. Gambetta, Conal E. Murray, Y.-K.-K. Fung, Douglas T. McClure, Oliver Dial, William Shanks, Jeffrey W. Sleight, Matthias Steffen

Published Nov 16, 2016• 120 citations
arXivHTMLPDF

Abstract

Superconducting qubits are sensitive to a variety of loss mechanisms including dielectric loss from interfaces. By changing the physical footprint of the qubit it is possible to modulate sensitivity to surface loss. Here we show a systematic study of planar superconducting transmons of differing physical footprints to optimize the qubit design for maximum coherence. We find that qubits with small footprints are limited by surface loss and that qubits with large footprints are limited by other loss mechanisms which are currently not understood.

DOI
10.1109/tasc.2016.2629670

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Superconducting qubits are sensitive to a variety of loss mechanisms including dielectric loss from interfaces. By changing the physical footprint of the qubit it is possible to modulate sensitivity to surface loss. Here we show a systematic study of planar superconducting transmons of differing physical footprints to optimize the qubit design for maximum coherence. We find that qubits with small footprints are limited by surface loss and that qubits with large footprints are limited by other loss mechanisms which are currently not understood.
Abstract Surface dielectric loss from superconducting transmon qubits is believed to be one of the dominant sources of decoherence. Reducing surface dielectric loss is crucial for achieving a high quality factor and a long relaxation time (T 1), which can be engineered by carefully changing the geometry of a transmon. In this paper, we present a shape-optimization approach to reduce surface dielectric loss in a transmon qubit. The capacitor pads and junction wires of transmons are shaped as spline curves and optimized through the finite-element method and a global optimization algorithm. We find that the participation ratio of capacitor pads and junction wires can be reduced by 15 % − 18 % and 22 % − 26 % compared to previous designs, while the overall footprint and anharmonicity are maintained at acceptable values. As a result, the two-level system-limited quality factor and the corresponding T 1 were increased by 21.6%.
State-of-the-art transmon qubits rely on large capacitors, which systematically improve their coherence due to reduced surface-loss participation. However, this approach increases both the footprint and the parasitic cross-coupling and is ultimately limited by radiation losses---a potential roadblock for scaling up quantum processors to millions of qubits. In this work we present transmon qubits with sizes as low as $36\phantom{\rule{0.2em}{0ex}}\ifmmode\times\else\texttimes\fi{}\phantom{\rule{0.2em}{0ex}}39\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}{\mathrm{m}}^{2}$ with $\ensuremath{\gtrsim}100$-nm-wide vacuum-gap capacitors that are micromachined from commercial silicon-on-insulator wafers and shadow evaporated with aluminum. We achieve a vacuum participation ratio up to 99.6% in an in-plane design that is compatible with standard coplanar circuits. Qubit relaxation-time measurements for small gaps with high zero-point electric field variance of up to 22 V/m reveal a double exponential decay indicating comparably strong qubit interaction with long-lived two-level systems. The exceptionally high selectivity of up to 20 dB to the superconductor-vacuum interface allows us to precisely back out the sub-single-photon dielectric loss tangent of aluminum oxide previously exposed to ambient conditions. In terms of future scaling potential, we achieve a ratio of qubit quality factor to a footprint area equal to $20\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}{\mathrm{m}}^{\ensuremath{-}2}$, which is comparable with the highest T1{T}_{1}T1​ devices relying on larger geometries, a value that could improve substantially for lower surface-loss superconductors.
Abstract Decoherence of superconducting transmon qubits is purported to be consistent with surface loss from two-level systems on the substrate surface. Here, we present a study of surface loss in transmon devices, explicitly designed to have varying sensitivities to different surface loss contributors. Our experiments also encompass two particular different sapphire substrates, which reveal the onset of a yet unknown additional loss mechanism outside of surface loss for one of the substrates. Tests across different wafers and devices demonstrate substantial variation, and we emphasize the importance of testing large numbers of devices for disentangling different sources of decoherence.
Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originate from Josephson junctions wiring and can limit qubit relaxation time. We experimentally extracted dielectric loss tangents of qubit elements and showed that dominant surface loss of wiring can occur for real qubits designs. Finally, we experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.
State-of-the-art transmon qubits rely on large capacitors which systematically improves their coherence due to reduced surface loss participation. However, this approach increases both the footprint and the parasitic cross-coupling and is ultimately limited by radiation losses - a potential roadblock for scaling up quantum processors to millions of qubits. In this work we present transmon qubits with sizes as low as 36$ \times 393939 μmmm^2$ with $\gtrsim$100 nm wide vacuum gap capacitors that are micro-machined from commercial silicon-on-insulator wafers and shadow evaporated with aluminum. After the release in HF vapor we achieve a vacuum participation ratio up to 99.6\% in an in-plane design that is compatible with standard coplanar circuits. Qubit relaxation time measurements for small gaps with high vacuum electric fields of up to 22 V/m reveal a double exponential decay indicating comparably strong coupling to long-lived two-level-systems (TLS). The exceptionally high selectivity of $>$20 dB to the superconductor-vacuum surface allows to precisely back out the sub-single-photon dielectric loss tangent of aluminum oxide exposed to ambient conditions. In terms of future scaling potential we achieve a qubit quality factor by footprint area of 20μs−220 μ\mathrm{s}^{-2}20μs−2, which is on par with the highest T1T_1T1​ devices relying on larger geometries and expected to improve substantially for lower loss superconductors like NbTiN, TiN or Ta.
The Josephson junction and shunt capacitor form a transmon qubit, which is the cornerstone of modern quantum computing platforms. For reliable quantum computing, it is important how long a qubit can remain in a superposition of quantum states, which is determined by the coherence time (T1). The coherence time of a qubit effectively sets the "lifetime" of usable quantum information, determining how long quantum computations can be performed before errors occur and information is lost. There are several sources of decoherence in transmon qubits, but the predominant one is generally considered to be dielectric losses in the natural oxide layer formed on the surface of the superconductor. In this paper, we present a numerical study of microwave surface losses in planar superconducting antennas of different transmon qubit designs. An asymptotic method for estimating the energy participation ratio in ultrathin films of nanometer scales is proposed, and estimates are given for the limits of achievable minimum RF losses depending on the electrical properties of the surface oxide and the interface of the qubit with the substrate material.