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arXiv:1209.6383 · Superconductor Science and Technology

Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation

Mark H. Volkmann, Anubhav Sahu, Coenrad Johann Fourie, Oleg A. Mukhanov

Published Nov 8, 2012• 154 citations
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Abstract

We report the first experimental demonstration of recently proposed energy efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic, eliminating the dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ∼0.8 aJ/bit operation. Two types of demonstration eSFQ circuit, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA cm −2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.

DOI
10.1088/0953-2048/26/1/015002

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We report the first experimental demonstration of recently proposed energy efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic, eliminating the dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ∼0.8 aJ/bit operation. Two types of demonstration eSFQ circuit, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA cm −2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.
We present the design and results of experimental verification methods for ultra-low-power digital circuits based on the recently introduced energy-efficient single flux quantum (eSFQ) logic. Similar to another low-power SFQ logic, ERSFQ, eSFQ circuits make use of superconducting dc bias current dividers and thus avoid static power dissipation. As a result, per-gate power dissipation is reduced by two orders of magnitude as compared to conventional rapid single flux quantum and static power dissipation is zero. The eSFQ circuits are fabricated using the HYPRES standard 4.5 kA/cm2process. We integrate a low-pass analog-to-digital modulator with our eSFQ deserializer to enable testing at high speed. In this paper, we demonstrate the viability and performance metrics of eSFQ circuits through functional and high-speed tests. Specifically, we confirmed correct operation and present measured parameter margins.
We designed and tested new energy-efficient single flux quantum (eSFQ) circuits. The eSFQ design approach is based on biasing logic gates via decision-making pairs (DMPs) which connect clock lines to synchronous gates. The eSFQ design of asynchronous gates is more challenging, since these gates are not clocked. We demonstrate eSFQ designs of asynchronous circuits and implemented two versions of eSFQ toggle flip-flops (eTFF) cells embedded in a synchronous shift register environment. The first design is based on the bias-free version of a TFF operating in the ballistic mode. In the second design, the TFFs dc bias is applied symmetrically, while the necessary half-quantum phase skew is achieved by magnetic flux bias, which can also be done with a pi-junction phase shifter. Surrounding shift registers are the eSFQ versions of the RSFQ shift register with two junctions per bit. In this work, we report the functional operation of these eSFQ circuits and their energy consumption.
Figures of merit connecting processing capabilities with power dissipated (OpS/Watt, Joule/bit, etc.) are becoming dominant factors in choosing technologies for implementing the next generation of computing and communication network systems. Superconductivity is viewed as a technology capable of achieving higher energy efficiencies than other technologies. Static power dissipation of standard RSFQ logic, associated with dc bias resistors, is responsible for most of the circuit power dissipation. In this paper, we review and compare different superconductor digital technology approaches and logic families addressing this problem. We present a novel energy-efficient single flux quantum logic family, ERSFQ/eSFQ. We also discuss energy-efficient approaches for output data interface and overall cryosystem design.
We have designed and tested energy-efficient single flux quantum (eSFQ) circuits for use in practical circuits. The first circuit is a 184-bit shift register for acquisition memory to store short transient events. The second circuit is a 16-bit deserializer integrated with an analog-to-digital converter modulator. The deserializer converts a high speed oversampling delta modulator 1-bit data stream into 16 parallel digital outputs at 1/16 of input data rate. In this work, we report preliminary functional and high-speed operation of some of these eSFQ circuits including their margins of operation at different clock speeds, maximum operation frequencies, and power dissipation.
We demonstrate rapid single-flux-quantum (RSFQ) circuits with reduced energy consumption by lowering the driving voltages and critical currents of Josephson junctions (JJs). At lowered voltages, the energy statically consumed by bias resistors (which is dominant in RSFQ circuits) is reduced. In addition, we show that when RSFQ circuits are driven by lowered constant voltages, the dynamic energy consumption resulting from the switching of JJs is reduced because of the suppression of the amplitudes of the signal voltage pulses, even though the switching speed becomes slower. Utilization of miniaturized JJs with smaller critical currents also leads to the reduction of static and dynamic energy consumption without decreasing the switching speed. We have designed and tested ultra-low-energy 8-bit shift registers, and verified the correctness of high-speed operations up to 18 GHz. The average energy consumption, including that at the bias resistors, was measured at 4.0 aJ/bit, which represents an energy efficiency two orders of magnitude better than that of standard RSFQ circuits.
We have designed and tested energy-efficient single flux quantum (eSFQ) circuits suitable for wave-pipelined architectures. The high energy-efficiency of eSFQ circuits combined with the sequential nature of SFQ logic makes eSFQ especially suitable for energy-efficient variants of highly-pipelined circuits such as modern arithmetic logic units (ALUs), without penalty to the clock speeds available to RSFQ logic. In previous work, we have demonstrated working eSFQ circuits in the form of shift registers, deserializers, counters. Here we expand on this work by introducing a means of moving data through eSFQ circuits without the need for buffering at every step, resembling the wave-pipelined architecture characterizing many large modern logic circuits. Specifically, we present a pipeline-friendly JTL, confluence buffer, and half adder, comprising the core components of many adder architectures. We also show how such an eSFQ full adder naturally lends itself to utilization in a computation pipeline. We report experimental demonstration of circuits manufactured in Hypres's 4.5 kA/cm2process.