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arXiv:cond-mat/0306265

Charge-based silicon quantum computer architectures using controlled single-ion implantation

Andrew S. Dzurak, Lloyd C. L. Hollenberg, David N. Jamieson, Fay E. Stanley, Changyi Yang, T. M. Buhler, V. Chan, D. J. Reilly, Cameron J. Wellard, A. R. Hamilton, Chris I. Pakes, Andrew J. Ferguson, E. Gauja, Steven Prawer, Gerard J Milburn, R. G. Clark

Published Jun 11, 2003• 8 citations

Abstract

We report a nanofabrication, control and measurement scheme for charge-based silicon quantum computing which utilises a new technique of controlled single ion implantation. Each qubit consists of two phosphorus dopant atoms ~50 nm apart, one of which is singly ionized. The lowest two energy states of the remaining electron form the logical states. Surface electrodes control the qubit using voltage pulses and dual single electron transistors operating near the quantum limit provide fast readout with spurious signal rejection. A low energy (keV) ion beam is used to implant the phosphorus atoms in high-purity Si. Single atom control during the implantation is achieved by monitoring on-chip detector electrodes, integrated within the device structure, while positional accuracy is provided by a nanomachined resist mask. We describe a construction process for implanted single atom and atom cluster devices with all components registered to better than 20 nm, together with electrical characterisation of the readout circuitry. We also discuss universal one- and two-qubit gate operations for this architecture, providing a possible path towards quantum computing in silicon.

DOI: 10.48550/arxiv.cond-mat/0306265

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The construction of micro- and nano-scale electronic devices that exploit the properties of single atoms have been proposed. A very promising device is a silicon based solid state quantum computer based on an array of single 31P atoms as qubits in a pure 28Si substrate. Operation of the device requires independent control, coupling and readout of the state of individual qubits. We have developed a construction strategy for a few qubit device based on ion implantation of the qubits into prefabricated cells. An ion energy of less than 20 keV is necessary to ensure the ion range is at the required depth in the substrate which is of the order of 20 nm. Single ion impacts are registered by the electrical transient induced in an external circuit. Electron Beam Lithography fabricated cells, containing electrodes of the required nanometre scale, have been implanted with 14 keV 31P ions and the pulse height spectrum of single ion impacts has been successfully recorded. Discrimination on the pulse height allows rejection of ions that suffer unacceptable straggling. This opens the way to the rapid construction of a two qubit device in the first instance that will test many of the essential mechanisms of a revolutionary solid state quantum computer.

Solid-state quantum computer architectures with qubits encoded using single atoms are now feasible given recent advances in the atomic doping of semiconductors. Here we present a charge qubit consisting of two dopant atoms in a semiconductor crystal, one of which is singly ionized. Surface electrodes control the qubit and a radio-frequency single-electron transistor provides fast readout. The calculated single gate times, of order 50 ps or less, are much shorter than the expected decoherence time. We propose universal one- and two-qubit gate operations for this system and discuss prospects for fabrication and scale up.

We discuss progress towards the fabrication and demonstration of a prototype silicon-based quantum computer. The devices are based on a precise array of 31P dopants embedded in 28Si. Fabrication is being pursued via two complementary pathways – a ‘top-down’ approach for near-term production of few-qubit demonstration devices and a ‘bottom-up’ approach for large-scale qubit arrays. The ‘top-down’ approach employs ion implantation through a multi-layer resist structure which serves to accurately register the donors to metal control gates and single-electron transistor (SET) read-out devices. In contrast the ‘bottom-up’ approach uses STM lithography and epitaxial silicon overgrowth to construct devices at an atomic scale. Techniques for qubit read-out, which utilise coincidence measurements on novel twin-SET devices, are also presented.

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