International Journal of Advanced Research in Computer Science

An Optimized Multiplier Using Reversible Logic Gates

H. R. Bhagyalakshmi, Venkatesha M.K

Published Jan 13, 2017• 1 citation

Abstract

Reversible logic is very essential for the construction of low power, low loss computational structures which are very essential for the construction of arithmetic circuits used in quantum computation, nano technology and other low power digital circuits. In this paper two designs of an optimized parallel multiplier circuit using reversible logic gates is presented. Multipliers are very essential for the construction of various computational units of a quantum computer. Duplication of operand bits are achieved using two gates namely BVF gate and CFO gate. The multiplier circuit uses DPG gates and a new 4 X 4 reversible logic gate called PPG gate. The proposed work is best compared to the other existing circuits. Keywords: Reversible logic circuits, Partial products, multiplier, quantum computing, Nanotechnology.

DOI: 10.26483/ijarcs.v3i4.1328

Related papers

Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates

H. R. Bhagyalakshmi

Reversible logic is an important area to carry the computation into the world of quantum computing.In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented.BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained.This reduces the total cost of the circuit.Toffoli gate is the universal and also most flexible reversible logic gate.So we have used the Toffoli gates to construct the designed multiplier.

International Journal of VLSI Design & Communication SystemsDec 31, 201221 citations

Two Novel Design Approaches for Optimized Reversible Multiplier Circuit

Sadia Afrin, Fahim Shihab Shan, Zarrin Tasnim Sworna

Reversible logic is one of the stepping stones in low power circuit design. Due to low power consumption and minimum bit loss features, future quantum computing devices are estimated to be reversible. Compared to addition, multiplication is a step further in the ladder of abstraction. It is the manifestation of a pattern generation system capable of representing 3-D patterns and transforming them by rotation, projection, reflection etc. The use of reversible logic in this field can reduce the wastage of energy, power and improve many factors. In this paper, an efficient multiplication algorithm has been proposed which is a modification of conventional shift-and-add multiplication method. Implementing proposed algorithm two reversible multiplier circuit has been proposed. For producing partial product, Peres gate has been used for the first design and Toffoli gate for the second design. Both of the circuits use Peres gate as Half-Adder and HNG gate as Full-Adder for addition of partial products. The first design is improved radically in terms of quantum cost, delay and the second design is notably improved in terms of transistor count and hardware complexity compared to the existing best known multipliers.

IEEE International WIE Conference on Electrical and Computer EngineeringNov 1, 20193 citations

A Novel Design of a Multiplier Using Reversible Ternary Gates

Mohammad Mehdi Panahi, Omid Hashemipour, Keivan Navi

Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.

IETE Journal of ResearchJan 30, 201921 citations

Optimization of multiplier in reversible logic

N. Bhuvaneswary, Adhi Lakshmi

Reversible logic is leading area in power consumption.Based on its application, its emerging trend in power consumption.In ideal situations, reversible circuit yield nil power.Different methods of multiplier optimized in this paper.Like quantum computers, multipliers required to develop computational units.In the paper, two different methods of multiplier developed with very large bit width.Based on partial products hierarchical method is developed.Another method is Karatsuba's algorithm developed based on divide and conquers method.Finally, we compare the results of both two methods.The projected reversible multipliers are enhanced in terms of quantum cost, number of constant inputs, number of garbage outputs and complexity in hardware.In nanotechnology applications this multiplier can be used to construct complex system.

3C Tecnología_Glosas de innovación aplicadas a la pymeNov 30, 20211 citation

Design of Dedicated Reversible Quantum Circuitry for Square Computation

H. V. Jayashree, Himanshu Thapliyal, Vinod Kumar Agrawal

Quantum computation is modeled by quantum circuits. All the quantum operations are reversible so the quantum circuits can be built using reversible logic gates. Reversible computing is the emerging technology, its major role is in the field of quantum computing, optical computing, and design of low power nanocircuits. The most frequently used computational unit for digital signal processing and multimedia applications is multiplier. To compute square of an operand, regular multipliers are used in general. This paper proposes a dedicated quantum circuit for computing square of an operand efficiently compared to the existing multipliers in the literature. The squaring unit is mathematically modeled and its metrics quantum cost, garbage outputs and ancilla input, gate count are calculated. We compared the proposed design with the existing multipliers to compute square and found that proposed square unit is efficient in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The proposed reversible square circuit has 63% to 85% improvement of quantum cost, garbage outputs, ancilla inputs and gate count over existing reversible multiplier circuits.

International Conference on VLSI DesignJan 1, 201413 citations

Design of a Quantum circuit for 4-Qubit multiplier using IBM Quantum Computer

A. Arunkumar Gudivada, Asisa Kumar Panigrahy

Abstract Reversible gates have been one of the emerging research areas in these days. The reversible gates have several applications in the fields of low power CMOS, DNA computing, optical, nanotechnology etc. Quantum computing is one of the fastest and upcoming nanotechnologies that can implement the digital logical circuits using reversible logic gates. In this paper, CNOT, TOFFOLI, FREDKIN and PERES reversible logic gates have been implemented on IBM quantum computer. An efficient one-bit full adder is going to be proposed using the reversible gates like CNOT and TOFFOLI. Later, a 4x4 multiplier will be developed using the proposed one-bit full adder. The proposed multiplier is proved to perform faster calculations compared to the earlier multipliers. The simulation of the presented modules will be done on IBM Quantum computer and the respective probabilities can be observed for different inputs.

Aug 4, 20220 citations