Reversible logic is an important area to carry the computation into the world of quantum computing.In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented.BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained.This reduces the total cost of the circuit.Toffoli gate is the universal and also most flexible reversible logic gate.So we have used the Toffoli gates to construct the designed multiplier.
Reversible logic is an important area to carry the computation into the world of quantum computing.In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented.BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained.This reduces the total cost of the circuit.Toffoli gate is the universal and also most flexible reversible logic gate.So we have used the Toffoli gates to construct the designed multiplier.
Reversible logic is very essential for the construction of low power, low loss computational structures which are very essential for the construction of arithmetic circuits used in quantum computation, nano technology and other low power digital circuits. In this paper two designs of an optimized parallel multiplier circuit using reversible logic gates is presented. Multipliers are very essential for the construction of various computational units of a quantum computer. Duplication of operand bits are achieved using two gates namely BVF gate and CFO gate. The multiplier circuit uses DPG gates and a new 4 X 4 reversible logic gate called PPG gate. The proposed work is best compared to the other existing circuits. Keywords: Reversible logic circuits, Partial products, multiplier, quantum computing, Nanotechnology.
Reversible logic is one of the stepping stones in low power circuit design. Due to low power consumption and minimum bit loss features, future quantum computing devices are estimated to be reversible. Compared to addition, multiplication is a step further in the ladder of abstraction. It is the manifestation of a pattern generation system capable of representing 3-D patterns and transforming them by rotation, projection, reflection etc. The use of reversible logic in this field can reduce the wastage of energy, power and improve many factors. In this paper, an efficient multiplication algorithm has been proposed which is a modification of conventional shift-and-add multiplication method. Implementing proposed algorithm two reversible multiplier circuit has been proposed. For producing partial product, Peres gate has been used for the first design and Toffoli gate for the second design. Both of the circuits use Peres gate as Half-Adder and HNG gate as Full-Adder for addition of partial products. The first design is improved radically in terms of quantum cost, delay and the second design is notably improved in terms of transistor count and hardware complexity compared to the existing best known multipliers.
Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.
Abstract Reversible gates have been one of the emerging research areas in these days. The reversible gates have several applications in the fields of low power CMOS, DNA computing, optical, nanotechnology etc. Quantum computing is one of the fastest and upcoming nanotechnologies that can implement the digital logical circuits using reversible logic gates. In this paper, CNOT, TOFFOLI, FREDKIN and PERES reversible logic gates have been implemented on IBM quantum computer. An efficient one-bit full adder is going to be proposed using the reversible gates like CNOT and TOFFOLI. Later, a 4x4 multiplier will be developed using the proposed one-bit full adder. The proposed multiplier is proved to perform faster calculations compared to the earlier multipliers. The simulation of the presented modules will be done on IBM Quantum computer and the respective probabilities can be observed for different inputs.
Multiplier circuits play an important role in reversible computation, which is helpful in diverse areas such as low power CMOS design, optical computing, DNA computing and bioinformatics. Here we propose a new reversible multiplier circuit with optimized hardware complexity. The optimized multiplier circuit is compared with the earlier proposals. We have shown that the quantum cost of earlier proposals can be further reduced with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule). A systematic protocol for reduction of quantum cost has been proposed. It has also been shown that the advantage in gate count obtained in some of the earlier proposals by introduction of new reversible gates is an artifact and if it is allowed then every circuit block can be reduced to a single gate. Further, it is shown that the 4x4 reversible gates proposed for designing of a component of multiplier circuit (full adder) is neither unique nor special and many such 4x4 gates may be proposed. As example three such new gates have been presented here and it is shown that the proposed gates are universal. It is also shown that the total cost of our design is minimum.
Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.