Real-time waveform generation supports dynamic quantum circuits without pre-storing complete waveforms for every execution path. However, long-lived distortions in flux-control lines degrade gate fidelity, requiring compensation to account for the actual pulse history. A frequency-domain inversion and time-domain fitting method is proposed for resource-efficient real-time flux distortion compensation. The method fits the reconstructed compensation impulse response with a compact hybrid infinite impulse response (IIR) and finite impulse response (FIR) filter. Look-ahead parallelization enables this filter to process synthesized waveforms at 1.2GSa/s on a field-programmable gate array (FPGA). Two-qubit cross-entropy benchmarking shows that real-time IIR filtering achieves a median controlled-Z Pauli fidelity close to the software-reference value of 99.57%. Numerical analysis and FPGA synthesis indicate approximately logarithmic growth in hardware resource use with compensation timescale. Extending compensation from microsecond to hundred-microsecond timescales increases look-up table (LUT) and digital signal processing (DSP) resource use by only about 14% and 4%, respectively, while maintaining a relative arithmetic error below
10−4. This work provides a scalable hardware foundation for high-fidelity flux control in dynamic superconducting quantum circuits.
Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We present the development of an open-source FPGA (field-programmable gate array) based processor for pulse-level qubit control. Our processor is designed primarily as an upgrade to QubiC, an open source qubit control platform, but can also be adapted to other systems. The processor is distributed in nature, with one core per arbitrary waveform generator (AWG); simplifying the design and allowing for straightforward scaling. Each processor core implements an instruction set consisting of timed pulse commands as well as simple arithmetic and branching instructions. Our design also includes interfaces for synchronizing the different cores and requesting/receiving (optionally processed) measurement results. Together, these features will allow a user to program arbitrary control flow within a quantum circuit based on previous measurement results. In this poster, we detail our design along with the expected resource utilization on the Xilinx Virtex 7 FPGA, and present pulse-level simulations of our system in the context of a simple feedback experiment.
We present a real-time FPGA decoder for a high-rate
[[512,174,8]] 3D product qLDPC code. We construct a circuit-level detector-error model for a compact syndrome-extraction schedule and propose a small parallel ensemble of row-wise serial min-sum decoders with cumulative memory. The decoder matches
BP+OSD-CS10 accuracy with one core and Relay-BP accuracy with three cores. The FPGA implementation meets the latency budget of neutral-atom and trapped-ion systems. An ASIC implementation would improve the latency, enabling real time decoding even for superconducting systems. At a physical error rate of
p=10−3, three FPGA devices decode 174 logical qubits with a logical error rate of
5×10−7 and effective distance 6. For
p=10−4, and assuming the number of BP iterations is capped to 30, the decoder's average latency is
5.1\textmu s and its worst-case latency is
97.9\textmu s.
This work presents QubiCML, a novel FPGA-based system engineered for real-time, in-situ discrimination of two- and three-level quantum states (quitrits) in superconducting quantum processors. Accurate and low-latency identification of quantum states is a critical enabler for scaling quantum computing, particularly as higher-dimensional systems such as qutrits are explored to increase information density, circuit depth, and gate expressivity. QubiCML integrates a lightweight, multi-layer neural network directly into FPGA hardware to classify the qutrit states
∣g⟩,∣e⟩, and
∣f⟩with high fidelity and minimal latency. Traditional state discrimination methods rely on offline post-processing, resulting in delays incompatible with the short coherence times of superconducting qubits. QubiCML overcomes this bottleneck by performing all inference operations within the FPGA fabric itself, achieving full quantum state discrimination within 66 ns (with softmax) or 40 ns (without softmax). The system supports fast reconfiguration via BRAM-stored parameters, enabling compatibility with varying quantum hardware and dynamic calibration environments. Additionally, we propose FPGA-friendly techniques for data normalization and fixed-point quantization to eliminate the overhead of floating-point and division operations—further optimizing the architecture for real-time deployment. We evaluate QubiCML on in-house superconducting hardware across multiple qubits and qutrits. The system achieves up to 97 % average accuracy for qutrits and up to 99 % for two-level systems, using readout windows as short as 650-750 ns. These results establish QubiCML as one of the first practical implementations of real-time qutrit state discrimination, marking an essential step toward mid-circuit measurements, dynamic feedback, and advanced error correction in higher-dimensional quantum computing.