We present a real-time FPGA decoder for a high-rate $[[512,174,8]]$ 3D product qLDPC code. We construct a circuit-level detector-error model for a compact syndrome-extraction schedule and propose a small parallel ensemble of row-wise serial min-sum decoders with cumulative memory. The decoder matches $\text{BP+OSD-CS}_\text{10}$ accuracy with one core and Relay-BP accuracy with three cores. The FPGA implementation meets the latency budget of neutral-atom and trapped-ion systems. An ASIC implementation would improve the latency, enabling real time decoding even for superconducting systems. At a physical error rate of $p=10^{-3}$, three FPGA devices decode 174 logical qubits with a logical error rate of $5\times10^{-7}$ and effective distance 6. For $p=10^{-4}$, and assuming the number of BP iterations is capped to 30, the decoder's average latency is $5.1\,$\textmu s and its worst-case latency is $97.9\,$\textmu s.
AI Summary
The paper asks whether high-rate qLDPC codes can be decoded under circuit-level noise within real-time hardware budgets without OSD or integer-programming post-processing. It studies the $[[512,174,8]]$ 3D product code, with a 34% encoding rate, and constructs a compact syndrome-extraction schedule and detector-error model.
The decoder combines row-wise serial normalized min-sum updates with cumulative memory and a parallel ensemble using different check-processing orders and perturbed priors. Numerical comparisons show one core matching BP+OSD-CS$_{10}$ accuracy and three cores matching Relay-BP accuracy for this code. Eight-round simulations give a per-logical-qubit, per-round logical error rate of approximately $5\times10^{-7}$ at $p=10^{-3}$ and observed scaling corresponding to effective distance 6. Fixed-point quantization produces little accuracy loss in the tested single-round setting.
One core is implemented and timed on an FPGA, taking $3.264\,\mu\mathrm{s}$ per iteration. At $p=10^{-4}$, its average latency is $5.1\,\mu\mathrm{s}$; a 30-iteration cap bounds core latency at $97.9\,\mu\mathrm{s}$. Each core occupies more than half the device’s BRAM, so the ensemble requires three FPGAs.
The hardware implementation decodes a single round without idling noise, rather than a repeated-round sliding window. Reported core timings exclude communication; the tested Ethernet interface adds $34\,\mu\mathrm{s}$. Multi-FPGA integration, sliding-window decoding, control-system integration, and quantization–resource trade-offs remain future work. Sub-microsecond ASIC operation is projected, not demonstrated, and superconducting implementation also faces the code’s long-range interaction requirements.
Little sign of AI-generated textOverclaimsStrong assumptions
Central claim may not hold: The implemented decoder handles a one-round task, whereas the repeated-round accuracy study uses a different task and continuous sliding-window decoding remains future work.
Only individual FPGA-core timing is demonstrated, not the integrated three-device ensemble with its selection and communication overhead.
The Z-basis terminal-measurement experiments establish basis-specific logical performance rather than protection of both complementary logical observables.
Sub-microsecond superconducting decoding remains an unvalidated ASIC extrapolation, and faster communication cannot make the measured 5.1-microsecond FPGA computation sub-microsecond.
The reported 5.1-microsecond average permits approximately 196 ensemble-decoded batches per millisecond before overhead, not the claimed more than 250.
Written by gpt-6.1-sol from the paper's full text. Automated: it can be wrong.
We present a real-time FPGA decoder for a high-rate [[512,174,8]] 3D product qLDPC code. We construct a circuit-level detector-error model for a compact syndrome-extraction schedule and propose a small parallel ensemble of row-wise serial min-sum decoders with cumulative memory. The decoder matches BP+OSD-CS10 accuracy with one core and Relay-BP accuracy with three cores. The FPGA implementation meets the latency budget of neutral-atom and trapped-ion systems. An ASIC implementation would improve the latency, enabling real time decoding even for superconducting systems. At a physical error rate of p=10−3, three FPGA devices decode 174 logical qubits with a logical error rate of 5×10−7 and effective distance 6. For p=10−4, and assuming the number of BP iterations is capped to 30, the decoder's average latency is 5.1\textmu s and its worst-case latency is 97.9\textmu s.
The paper asks whether high-rate qLDPC codes can be decoded under circuit-level noise within real-time hardware budgets without OSD or integer-programming post-processing. It studies the [[512,174,8]] 3D product code, with a 34% encoding rate, and constructs a compact syndrome-extraction schedule and detector-error model.
The decoder combines row-wise serial normalized min-sum updates with cumulative memory and a parallel ensemble using different check-processing orders and perturbed priors. Numerical comparisons show one core matching BP+OSD-CS10 accuracy and three cores matching Relay-BP accuracy for this code. Eight-round simulations give a per-logical-qubit, per-round logical error rate of approximately 5×10−7 at p=10−3 and observed scaling corresponding to effective distance 6. Fixed-point quantization produces little accuracy loss in the tested single-round setting.
One core is implemented and timed on an FPGA, taking 3.264μs per iteration. At p=10−4, its average latency is 5.1μs; a 30-iteration cap bounds core latency at 97.9μs. Each core occupies more than half the device’s BRAM, so the ensemble requires three FPGAs.
The hardware implementation decodes a single round without idling noise, rather than a repeated-round sliding window. Reported core timings exclude communication; the tested Ethernet interface adds 34μs. Multi-FPGA integration, sliding-window decoding, control-system integration, and quantization–resource trade-offs remain future work. Sub-microsecond ASIC operation is projected, not demonstrated, and superconducting implementation also faces the code’s long-range interaction requirements.
Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by 3.1× and 6.5×. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate p=10−3, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at 1μs average latency, and by 13% under a strict 1μs deadline.
Real-time quantum error correction requires classical decoders to process growing syndrome workloads with low and predictable latency. For quantum low-density parity-check (qLDPC) codes, iterative belief propagation (BP) repeatedly updates messages over sparse Tanner graphs, creating substantial memory-access and data-movement demands. We map normalized Min-Sum BP decoding of the [[144,12,12]] Bivariate Bicycle qLDPC code onto a DPU-based Processing-in-Memory (PIM) architecture. Within each DPU, 11 tasklets cooperatively decode one syndrome, while multiple DPUs process independent syndrome instances in parallel. Using uPIMulator and a data-qubit Pauli error model with ideal syndrome measurements, we compare throughput, per-syndrome processing time, logical error rate (LER), and single-syndrome tail latency against a 16-logical-CPU baseline. At a component-wise physical error probability of p=0.001 and one BP iteration, the projected aggregate kernel throughput of 2,560 DPUs reaches 1.071 x 10^7 decodes/s, compared with 1.22 x 10^6 decodes/s for the CPU, an 8.8x improvement. From two iterations onward, the measured LER remains below the physical error probability for every evaluated value of p. For one to five iterations, the maximum sampled serialized X+Z DPU compute latency remains below the 1 ms decoder-side reference for trapped-ion QEC, reaching approximately 0.873 ms at five iterations. These results show that near-memory processing can provide high aggregate throughput and sub-millisecond compute latency for qLDPC BP decoding under the evaluated conditions.
Quantum low-density parity-check (qLDPC) decoding requires reliable corrections and low latency over long syndrome histories. We extend BP-SF, an oscillation-guided belief-propagation (BP) decoder with independent syndrome-flip trials, by introducing windowed and streaming operations. Our CUDA implementation combines disordered-memory retries, sliding windows, correlation-aware graphs, and layered scheduling. Circuit-level simulations test fixed-basis memory and complete logical Pauli-frame recovery. On the [[144,12,12]] bivariate bicycle code at physical error rate p = 0.002, parallel BP-SF reduces 99.9th-percentile call latency by a factor of 13.15 relative to an eight-chain Relay-BP GPU baseline on 100,000 matched samples for which every tested method's initial BP stage fails within 80 iterations. Windowed BP-SF maintains a flat logical error rate and nearly constant per-round compute time through 512 rounds, reaching a 17.1-fold speedup over monolithic decoding. In 512-round full-frame streaming decoding with 2.97-ms syndrome arrivals, layered BP-SF on a transformed joint graph with 20 retries reduces 99.9th-percentile correction-release age from 166.29 to 36.25 ms relative to the joint graph with flooding updates and 100 retries. These results connect parallel BP post-processing to lower decoding costs and earlier correction release in streaming quantum memory.
We propose a decoder for quantum low density parity check (LDPC) codes based on a beam search heuristic guided by belief propagation (BP). Our beam search decoder applies to all quantum LDPC codes and achieves different speed-accuracy tradeoffs by tuning its parameters such as the beam width. We perform numerical simulations under circuit level noise for the [[144,12,12]] bivariate bicycle (BB) code at noise rate p=10−3 to estimate the logical error rate and the 99.9 percentile runtime and we compare with the BP-OSD decoder which has been the default quantum LDPC decoder for the past six years. A variant of our beam search decoder with a beam width of 64 achieves a 17× reduction in logical error rate. With a beam width of 8, we reach the same logical error rate as BP-OSD with a 26.2× reduction in the 99.9 percentile runtime. We identify the beam search decoder with beam width of 32 as a promising candidate for trapped ion architectures because it achieves a 5.6× reduction in logical error rate with a 99.9 percentile runtime per syndrome extraction round below 1ms at p=5×10−4. Remarkably, this is achieved in software on a single core, without any parallelization or specialized hardware (FPGA, ASIC), suggesting one might only need three 32-core CPUs to decode a trapped ion quantum computer with 1000 logical qubits.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration.
To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits.
Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Abstract In practical quantum error correction implementations, the measurement of syndrome information is an unreliable step—typically modeled as a binary measurement outcome flipped with some probability. However, the measured syndrome is in fact a discretized value of the continuous voltage or current values obtained in the physical implementation of the syndrome extraction. In this paper, we use this “soft” or analog information to benefit iterative decoders for decoding quantum low-density parity-check (QLDPC) codes. Syndrome-based iterative belief propagation decoders are modified to utilize the soft syndrome to correct both data and syndrome errors simultaneously. We demonstrate the advantages of the proposed scheme not only in terms of comparison of thresholds and logical error rates for quasi-cyclic lifted-product QLDPC code families but also with faster convergence of iterative decoders. Additionally, we derive hardware (FPGA) architectures of these soft syndrome decoders and obtain similar performance in terms of error correction to the ideal models even with reduced precision in the soft information. The total latency of the hardware architectures is about 600 ns (for the QLDPC codes considered) in a 20 nm CMOS process FPGA device, and the area overhead is almost constant—less than 50% compared to min-sum decoders with noisy syndromes.