Abstract Energy participation ratio (EPR) at the metal-substrate (MS) interface is a dominant decoherence source limiting the coherence time ( T 1 ) of planar superconducting transmon qubits. Traditional EPR simulations rely on idealized geometric models, ignoring process-induced morphological deviations that significantly impact actual device performance. To bridge this gap, we propose a unified data-driven framework. It automatically extracts geometric parameters from SEM cross-sections using computer vision (CV). These parameters are then imported into a calibrated 2D EPR simulation model. Sobol global sensitivity analysis is further applied to quantify the influences of key parameters. Parametric simulations reveal that the EPR scaling factor F ms generally decreases with increasing interface thickness, substrate over-etch depth, and trench angle, driven by mitigated edge electric field crowding. Sobol analysis further identifies substrate over-etch depth and trench angle as the dominant drivers of F ms , with a significant synergistic interaction between these two parameters. Evaluations across eight process-feasible geometric configurations indicate that thin interface layer combined with a deep substrate over-etch yields the largest predict reduction in interface EPR, corresponding to a projected relative enhancement in T 1 under the assumption of a constant interface loss tangent. We derive actionable process guidelines for planar Al-on-Si transmon qubits, prioritizing the co-tuning of trench parameters to balance MS-interface EPR reduction with manufacturing feasibility within the investigated parameter range. This framework provides a systematic pipeline for incorporating process-induced geometric deviations into EPR prediction, and offers a design-stage simulation tool applicable to planar superconducting structures with similar coplanar edge-dominated EPR characteristics.
Abstract Energy participation ratio (EPR) at the metal-substrate (MS) interface is a dominant decoherence source limiting the coherence time ( T 1 ) of planar superconducting transmon qubits. Traditional EPR simulations rely on idealized geometric models, ignoring process-induced morphological deviations that significantly impact actual device performance. To bridge this gap, we propose a unified data-driven framework. It automatically extracts geometric parameters from SEM cross-sections using computer vision (CV). These parameters are then imported into a calibrated 2D EPR simulation model. Sobol global sensitivity analysis is further applied to quantify the influences of key parameters. Parametric simulations reveal that the EPR scaling factor F ms generally decreases with increasing interface thickness, substrate over-etch depth, and trench angle, driven by mitigated edge electric field crowding. Sobol analysis further identifies substrate over-etch depth and trench angle as the dominant drivers of F ms , with a significant synergistic interaction between these two parameters. Evaluations across eight process-feasible geometric configurations indicate that thin interface layer combined with a deep substrate over-etch yields the largest predict reduction in interface EPR, corresponding to a projected relative enhancement in T 1 under the assumption of a constant interface loss tangent. We derive actionable process guidelines for planar Al-on-Si transmon qubits, prioritizing the co-tuning of trench parameters to balance MS-interface EPR reduction with manufacturing feasibility within the investigated parameter range. This framework provides a systematic pipeline for incorporating process-induced geometric deviations into EPR prediction, and offers a design-stage simulation tool applicable to planar superconducting structures with similar coplanar edge-dominated EPR characteristics.
An accurate and efficient numerical electromagnetic model for superconducting qubits is essential for characterizing and minimizing design-dependent dielectric losses. The energy participation ratio (EPR) is the commonly adopted metric used to evaluate these losses, but its calculation presents a severe multiscale computational challenge. Conventional finite element method (FEM) requires 3D volumetric meshing, leading to prohibitive computational costs and memory requirements when attempting to capture singular electric fields at nanometer-thin material interfaces. To address this bottleneck, we propose SesQ, a surface integral equation simulator tailored for the precise simulation of the EPR. By applying discretization on 2D surfaces, deriving a semi-analytical multilayer Green's function, and employing a dedicated non-conformal boundary mesh refinement scheme, SesQ accurately resolves singular edge fields without an explosive growth in the number of unknowns. Validations with analytically solvable models demonstrate that SesQ accelerates capacitance extraction by roughly two orders of magnitude compared to commercial FEM tools. While achieving comparable accuracy for capacitance extraction, SesQ delivers superior precision for EPR calculation. Simulations of practical transmon qubits further reveal that FEM approaches tend to significantly underestimate the EPR. Finally, the high efficiency of SesQ enables rapid iteration in the layout optimization, as demonstrated by minimizing the EPR of the qubit pattern, establishing the simulator as a powerful tool for the automated design of low-loss superconducting quantum circuits.
Dielectric loss due to two-level systems is a limiting factor for superconducting qubit relaxation times. These losses arise mostly from nanometer-scale interfacial defect regions in superconducting devices with planar dimensions of microns to millimeters, thus making it resource intensive to accurately simulate the electric field density in these regions with traditional electromagnetic solvers. In this work, we demonstrate a fast boundary integral equation solver that allows precise simulation of electric field density in these thin regions, showing a speedup of around two orders of magnitude over traditional solvers, with relative errors around 10−7 for a ten-minute solution runtime. By computing participation ratios through Green's first identity without squaring the electric field, our approach is less susceptible to the field singularities near conductor corners. We apply this solver to a basic untrenched coplanar waveguide cross-section, showing that the common assumption of participation ratio linearity with dielectric constant holds well for some interfaces and not others; in particular, while the metal-air (MA) top and corner follow this linear relationship strongly, the MA sidewall does not. We then compare isotropic and anisotropic etching, showing that the MA sidewall and the metal-air-substrate triple junction are the most strongly affected. We are currently leveraging this solver to explore geometries that will uniquely isolate the participation ratios of the different dielectrics. Finally, we are working to combine this solver framework with a full 3D microwave solver to accurately calculate participation ratios for the thin dielectrics that are known sources of loss in superconducting qubits.
Quantum computers are devices that use quantum phenomena for information processing, with the advantage of solving specific problems faster than classical computers. Superconducting circuits with Josephson junctions have emerged as one of the most promising platforms for large-scale quantum computing in the last decade. However, in the current noisy intermediate-scale quantum era, circuits and algorithms suffer from low fidelities and limited amount of superconducting quantum bits, or qubits. Short coherence times owing to undesired transitions between the excited and ground states of a qubit, are one of the primary sources of error. This work studies the contribution of losses arising from two-level systems, localized predominantly in material interfaces, on the coherence time for conventional superconducting-qubit geometries. This is accomplished by using the method of energy participation ratios with electromagnetic finite-element-method simulations. First, we compare energy participations in two-dimensional cross-sections to those in a similar three-dimensional environment with a thin-sheet approximation for metal thickness and no modelling of lossy material interfaces. After validating the approximations, the method of energy participation ratios is further applied to analyze real-world qubit designs, demonstrating how the approach can facilitate the development of high-coherence superconducting quantum devices. Individual design parameter sweeps are also conducted to provide insight into dependencies on the geometry. We discover that the electric field is concentrated near the Josephson junction area, and the resulting participations are primarily influenced by the lengths of etched gaps between metals in a chip. A Bayesian machine-learning-based optimizer is introduced to systematically discover design geometries that improve qubit relaxation time. This approach is applied to a modified version of a common qubit geometry defined by splines. Furthermore, the workflow is implemented in KQCircuits, a GPLv3-licensed open-source layout design tool for designing state-of-the-art superconducting circuits and processors.
This work presents a comprehensive analytical and simulation-based study of superconducting quantum chip architectures, spanning both 2D planar and 3D-integrated designs. We first design and simulate a planar quantum chip layout using Qiskit Metal, which is imported into Ansys HFSS (High Frequency Structure Simulator) to construct a 3D model and perform electromagnetic simulations. A detailed analysis using Driven Modal, Eigenmode, Magnetostatic, and Q3D Capacitance Extraction solvers ensures our simulations accurately reflect physical behavior. The results are validated against analytical models from microwave engineering. pyEPR (Python Energy Participation Ratio) is used to extract key quantum metrics, including eigenfrequencies, quality factors, decoherence times, anharmonicity, cross-Kerr interactions, and participation ratios. Building on this planar design, we extend our study to a 3D-integrated flip-chip architecture featuring two superconducting qubits fabricated on separate high-resistivity silicon substrates. Using HFSS and analytical modeling, we show that detuned qubits maintain stable eigenfrequencies, quality factors, decoherence times, anharmonicity, and cross-Kerr interactions over varying substrate separation values. However, the introduction of dielectric loss tangents reduces quality factors which degrades coherence times and introduces an additional dephasing. These findings highlight the potential of 3D quantum integration, given minimal material imperfections.The planar and 3D designs together form a cohesive investigation into next-generation quantum hardware, with the 2D layout currently taped-out and under fabrication.
Quantum computing is advancing rapidly, with superconducting quantum computing (SQC) emerging as one of the most promising platforms for scalable quantum information processing. In contrast to fabrication-focused approaches prevalent in current literature, this work presents a fully simulation-based design and tuning methodology for a small-scale superconducting quantum chip - addressing practical limitations posed by fabrication resource constraints - and consequently excludes physical chip fabrication or real-time performance evaluation (e.g., fidelity and error rate measurements). A meticulous, step-by-step electromagnetic simulation was conducted on the chip, designed using Qiskit Metal and Ansys Electronics, with qubit parameters tuned and verified using the Lumped Oscillator Model (LOM) and Energy Participation Ratio (EPR) methods. The design achieves good parameter convergence with relative tuning error rates (Δ%) below 0.05% after 15 adaptive passes and approximately 50,000 solved mesh elements, yielding an Energy Participation Ratio (EPR) of 91.8 % for the chip substrate (Silicon). Furthermore, the study includes a theoretical comparison between two fundamental qubit-qubit coupling schemes. A key contribution of this work lies in systematically analyzing how geometric variations in qubit design affect critical quantum parameters such as qubit frequencies, anharmonicities, coupling strengths, and dispersive shifts - thereby offering a comprehen-sive, simulation-driven framework for early-stage quantum chip prototyping.
Superconducting qubits are sensitive to a variety of loss mechanisms, which include dielectric loss from interfaces. The calculation of participation near the key interfaces of planar designs can be accomplished through an analytical description of the electric field density based on conformal mapping. In this way, a 2-D approximation to coplanar waveguide and capacitor designs produces values of the participation as a function of depth from the top metallization layer as well as the volume participation within a given thickness from this surface by reducing the problem to a surface integration over the region of interest. These quantities are compared to finite-element method numerical solutions, which validate the values at large distances from the coplanar metallization but diverge near the edges of the metallization features due to the singular nature of the electric fields. A simple approximation to the electric field energy at shallow depths (relative to the waveguide width) is also presented that closely replicates the numerical results based on conformal mapping and those reported in prior literature. These techniques are applied to the calculation of surface participation within a transmon qubit design, where the effects due to shunting capacitors can be easily integrated with those associated with metallization comprising the local environment of the qubit junction.