Quantum computers are devices that use quantum phenomena for information processing, with the advantage of solving specific problems faster than classical computers. Superconducting circuits with Josephson junctions have emerged as one of the most promising platforms for large-scale quantum computing in the last decade. However, in the current noisy intermediate-scale quantum era, circuits and algorithms suffer from low fidelities and limited amount of superconducting quantum bits, or qubits. Short coherence times owing to undesired transitions between the excited and ground states of a qubit, are one of the primary sources of error. This work studies the contribution of losses arising from two-level systems, localized predominantly in material interfaces, on the coherence time for conventional superconducting-qubit geometries. This is accomplished by using the method of energy participation ratios with electromagnetic finite-element-method simulations. First, we compare energy participations in two-dimensional cross-sections to those in a similar three-dimensional environment with a thin-sheet approximation for metal thickness and no modelling of lossy material interfaces. After validating the approximations, the method of energy participation ratios is further applied to analyze real-world qubit designs, demonstrating how the approach can facilitate the development of high-coherence superconducting quantum devices. Individual design parameter sweeps are also conducted to provide insight into dependencies on the geometry. We discover that the electric field is concentrated near the Josephson junction area, and the resulting participations are primarily influenced by the lengths of etched gaps between metals in a chip. A Bayesian machine-learning-based optimizer is introduced to systematically discover design geometries that improve qubit relaxation time. This approach is applied to a modified version of a common qubit geometry defined by splines. Furthermore, the workflow is implemented in KQCircuits, a GPLv3-licensed open-source layout design tool for designing state-of-the-art superconducting circuits and processors.
Quantum computers are devices that use quantum phenomena for information processing, with the advantage of solving specific problems faster than classical computers. Superconducting circuits with Josephson junctions have emerged as one of the most promising platforms for large-scale quantum computing in the last decade. However, in the current noisy intermediate-scale quantum era, circuits and algorithms suffer from low fidelities and limited amount of superconducting quantum bits, or qubits. Short coherence times owing to undesired transitions between the excited and ground states of a qubit, are one of the primary sources of error. This work studies the contribution of losses arising from two-level systems, localized predominantly in material interfaces, on the coherence time for conventional superconducting-qubit geometries. This is accomplished by using the method of energy participation ratios with electromagnetic finite-element-method simulations. First, we compare energy participations in two-dimensional cross-sections to those in a similar three-dimensional environment with a thin-sheet approximation for metal thickness and no modelling of lossy material interfaces. After validating the approximations, the method of energy participation ratios is further applied to analyze real-world qubit designs, demonstrating how the approach can facilitate the development of high-coherence superconducting quantum devices. Individual design parameter sweeps are also conducted to provide insight into dependencies on the geometry. We discover that the electric field is concentrated near the Josephson junction area, and the resulting participations are primarily influenced by the lengths of etched gaps between metals in a chip. A Bayesian machine-learning-based optimizer is introduced to systematically discover design geometries that improve qubit relaxation time. This approach is applied to a modified version of a common qubit geometry defined by splines. Furthermore, the workflow is implemented in KQCircuits, a GPLv3-licensed open-source layout design tool for designing state-of-the-art superconducting circuits and processors.
Dielectric loss due to two-level systems is a limiting factor for superconducting qubit relaxation times. These losses arise mostly from nanometer-scale interfacial defect regions in superconducting devices with planar dimensions of microns to millimeters, thus making it resource intensive to accurately simulate the electric field density in these regions with traditional electromagnetic solvers. In this work, we demonstrate a fast boundary integral equation solver that allows precise simulation of electric field density in these thin regions, showing a speedup of around two orders of magnitude over traditional solvers, with relative errors around 10−7 for a ten-minute solution runtime. By computing participation ratios through Green's first identity without squaring the electric field, our approach is less susceptible to the field singularities near conductor corners. We apply this solver to a basic untrenched coplanar waveguide cross-section, showing that the common assumption of participation ratio linearity with dielectric constant holds well for some interfaces and not others; in particular, while the metal-air (MA) top and corner follow this linear relationship strongly, the MA sidewall does not. We then compare isotropic and anisotropic etching, showing that the MA sidewall and the metal-air-substrate triple junction are the most strongly affected. We are currently leveraging this solver to explore geometries that will uniquely isolate the participation ratios of the different dielectrics. Finally, we are working to combine this solver framework with a full 3D microwave solver to accurately calculate participation ratios for the thin dielectrics that are known sources of loss in superconducting qubits.
Abstract Energy participation ratio (EPR) at the metal-substrate (MS) interface is a dominant decoherence source limiting the coherence time ( T 1 ) of planar superconducting transmon qubits. Traditional EPR simulations rely on idealized geometric models, ignoring process-induced morphological deviations that significantly impact actual device performance. To bridge this gap, we propose a unified data-driven framework. It automatically extracts geometric parameters from SEM cross-sections using computer vision (CV). These parameters are then imported into a calibrated 2D EPR simulation model. Sobol global sensitivity analysis is further applied to quantify the influences of key parameters. Parametric simulations reveal that the EPR scaling factor F ms generally decreases with increasing interface thickness, substrate over-etch depth, and trench angle, driven by mitigated edge electric field crowding. Sobol analysis further identifies substrate over-etch depth and trench angle as the dominant drivers of F ms , with a significant synergistic interaction between these two parameters. Evaluations across eight process-feasible geometric configurations indicate that thin interface layer combined with a deep substrate over-etch yields the largest predict reduction in interface EPR, corresponding to a projected relative enhancement in T 1 under the assumption of a constant interface loss tangent. We derive actionable process guidelines for planar Al-on-Si transmon qubits, prioritizing the co-tuning of trench parameters to balance MS-interface EPR reduction with manufacturing feasibility within the investigated parameter range. This framework provides a systematic pipeline for incorporating process-induced geometric deviations into EPR prediction, and offers a design-stage simulation tool applicable to planar superconducting structures with similar coplanar edge-dominated EPR characteristics.
Quantum computing aims to leverage the principles of quantum mechanics to achieve superior information processing capabilities beyond the limits of today's computers. These machines have the potential to efficiently simulate quantum mechanical systems, revolutionizing the development of new materials, drug discovery, and fundamental physics research. Additionally, algorithms such as prime factorization and unstructured data search offer significant speed-ups on quantum computers, enhancing computational capabilities beyond current limits. The first experimental demonstrations of this central idea have sparked significant excitement and expectation in society. Superconducting circuit hardware technologies, which implement quantum computers, are rapidly maturing and transitioning from physics laboratories to industrial fabrication plants. This work aims to bridge the gap between physics laboratory fabrication techniques and industrial standards. Here, the approach starts from complementary metal-oxide-semiconductor (CMOS) compatible processes, optimized using insights from the decades of laboratory development. In particular, two alternative Josephson junction (JJ) fabrication methods are explored, the overlap junction and tri-layer junction approaches, that do not rely on the standard angled evaporation and lift-off processes. These CMOS-compatible fabrication processes are benchmarked for quality and uniformity, using superconducting resonators and qubits to probe material defects and process variability. Device metrics are used to identify and optimize the most critical fabrication steps. Using these methods, a successful overlap JJ qubit fabrication flow is demonstrated with industry standard tools on 300 mm wafer scale, achieving an initial qubit yield of 98.25%. Several devices exhibit lifetimes and coherence times exceeding 100 microseconds, comparable to state-of-the-art devices. Extensive across-wafer measurements and analysis provide insights into limiting factors such as material defects at device interfaces, identifying avenues for continued improvements. The second method, the tri-layer JJ approach, has the potential for defect-free devices with CMOS-grade uniformity by growing epitaxial junctions, patterned with advanced lithography and dry-etch techniques. However, subsequent metallization steps introduce detrimental microwave losses compromising the pristine junctions. Here, a novel tri-layer qubit design is proposed, the tri-layer merged element transmon (tri-MET), which eliminates further processing beyond pristine junction deposition and patterning. The new device is demonstrated in simulation, and initial fabrication steps are presented. In summary, this thesis presents key breakthroughs in superconducting qubit fabrication methods, providing evidence for the viability of industrial methods to fabricate high-coherence superconducting qubits. Further work will focus on addressing interface defects, improving junction uniformity, and incorporating three-dimensional integration techniques to enable large-scale quantum processors for computations beyond the classical limits.
Quantum computing is advancing rapidly, with superconducting quantum computing (SQC) emerging as one of the most promising platforms for scalable quantum information processing. In contrast to fabrication-focused approaches prevalent in current literature, this work presents a fully simulation-based design and tuning methodology for a small-scale superconducting quantum chip - addressing practical limitations posed by fabrication resource constraints - and consequently excludes physical chip fabrication or real-time performance evaluation (e.g., fidelity and error rate measurements). A meticulous, step-by-step electromagnetic simulation was conducted on the chip, designed using Qiskit Metal and Ansys Electronics, with qubit parameters tuned and verified using the Lumped Oscillator Model (LOM) and Energy Participation Ratio (EPR) methods. The design achieves good parameter convergence with relative tuning error rates (Δ%) below 0.05% after 15 adaptive passes and approximately 50,000 solved mesh elements, yielding an Energy Participation Ratio (EPR) of 91.8 % for the chip substrate (Silicon). Furthermore, the study includes a theoretical comparison between two fundamental qubit-qubit coupling schemes. A key contribution of this work lies in systematically analyzing how geometric variations in qubit design affect critical quantum parameters such as qubit frequencies, anharmonicities, coupling strengths, and dispersive shifts - thereby offering a comprehen-sive, simulation-driven framework for early-stage quantum chip prototyping.
An accurate and efficient numerical electromagnetic model for superconducting qubits is essential for characterizing and minimizing design-dependent dielectric losses. The energy participation ratio (EPR) is the commonly adopted metric used to evaluate these losses, but its calculation presents a severe multiscale computational challenge. Conventional finite element method (FEM) requires 3D volumetric meshing, leading to prohibitive computational costs and memory requirements when attempting to capture singular electric fields at nanometer-thin material interfaces. To address this bottleneck, we propose SesQ, a surface integral equation simulator tailored for the precise simulation of the EPR. By applying discretization on 2D surfaces, deriving a semi-analytical multilayer Green's function, and employing a dedicated non-conformal boundary mesh refinement scheme, SesQ accurately resolves singular edge fields without an explosive growth in the number of unknowns. Validations with analytically solvable models demonstrate that SesQ accelerates capacitance extraction by roughly two orders of magnitude compared to commercial FEM tools. While achieving comparable accuracy for capacitance extraction, SesQ delivers superior precision for EPR calculation. Simulations of practical transmon qubits further reveal that FEM approaches tend to significantly underestimate the EPR. Finally, the high efficiency of SesQ enables rapid iteration in the layout optimization, as demonstrated by minimizing the EPR of the qubit pattern, establishing the simulator as a powerful tool for the automated design of low-loss superconducting quantum circuits.
The development of quantum computers, capable of surpassing classical computing in solving specific complex problems, hinges on breakthroughs in materials science, precision device fabrication, and the optimization of quantum architectures [1]. Among the leading candidates for quantum computation, superconducting qubits, particularly those based on transmon designs, have shown promising advances with coherence times reaching hundreds of microseconds [2]. However, to fully unlock the potential of scalable quantum computing, further enhancements in coherence are necessary. The intricate structure-coherence relationship within these devices, especially at critical interfaces such as metal-air, metal-dielectric, and metal-substrate in Josephson junctions (JJs), poses a significant challenge due to the potential for two-level-system loss channels. Here, we detail our pioneering efforts to understand these structure-coherence relationships utilizing advanced electron microscopy techniques. Focusing on the Al-AlOx and Al-Si substrate interfaces in Josephson Junctions, we employ a combination of low-loss and core-loss electron energy loss spectroscopy (EELS) and four-dimensional scanning transmission electron microscopy (4D-STEM) conducted at room and ultra-low temperatures (sub-6 K). This approach allows for an unprecedented examination of the chemical composition, bonding environments, and nanoscale structures of key surfaces and interfaces critical to the quantum coherence. Figure 1 presents a typical superconducting architecture at the chip level; each superconducting qubit consists of a Josephson Junction in parallel with an ultra-low-loss capacitor to create a resonant structure in the 3-6GHz range. JJs are highlighted in the area boxed in Fig. 1A and can be observed in detail in Fig. 1B. Lamella cross-sections (as shown in Fig. 1C) were prepared using a dual-beam focused ion beam (FIB) FEI-SEM Helios Nanolab. The lift-off was performed using 30 kV Ga+ ions, and the final cleaning step was carried out at 2 kV to remove surface damage on the area of interest, resulting in a final sample thickness of 50-100 nm. Transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) data were collected on a probe-corrected JEOL ARM200 S/TEM operating at 200 kV. The convergent angle for ADF-STEM imaging was 25 mrad. Electron energy loss spectra (EELS) were acquired at 200 kV using a Gatan GIF Quantum on a K2 pixelated detector. Data processing (background subtraction, plural scattering removal, and signal mapping) was conducted using Gatan GMS software. Four-dimensional STEM (4D-STEM) data were collected by a K3 and STELA cameras. The convergent angles were 0.5-1.5 mrad, and the camera length was 6-10 cm. The step size was 5-10 Å. Merging microscopic insights with electrical data and theoretical frameworks, we aim to reveal how atomic-scale irregularities affect coherence times. Our results highlight key decoherence mechanisms in superconducting qubits and suggest specific improvements for qubit design and manufacturing. By linking electron microscopy findings to device performance, we outline strategies to reduce decoherence, essential for achieving reliable quantum computing. This work bridges materials science and quantum engineering, driving efforts in making scalable quantum computers forward [3]. A) Microscopic view of a superconducting transmon qubit, highlighting its symmetric design with central island and capacitor pads. B) SEM image of a JJ displaying their Al top and bottom contacts. C) STEM image of a JJ showing its key components and interfaces: Al top and bottom contact, AlOx tunnel barrier, Si substrate and Al-Si interface. A) EELS chemical maps of two interfaces, Al/Al and Al/Si using K-edges of oxygen, aluminum and silicon of a Josephson junction. It is possible to detect a formation of oxides at both interfaces. Plots showing Al and Si K-edge at 1560 eV and 1839 eV, respectively, and the ELNES are shown on the right side (Scale bar in A – 20 nm). B) Analysis of the disordered Al phases at the interfaces utilizing ePDF.