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International Journal of Computational Intelligence and Applications

Low-Latency and High-Efficient Multi-Kernel Polar Encoding with Deep Deterministic Policy Gradient for Successive Cancellation Decoder

yamini pushpa banda, Sunita Panda

Published Jul 4, 2026• 0 citations
Publisher

Abstract

Multi-Kernel Polar Codes (MKPCs) play a crucial role in extending the flexibility of polar code construction. Combining different kernel matrices enables a wider range of block lengths and greater adaptability to various communication scenarios while preserving the polarization effect. However, polar codes often suffer from limited scalability and poor error-rate performance at short block lengths, which affects their decoding performance. To overcome these drawbacks, a Successive Cancellation (SC) decoder based on the Deep Deterministic Policy Gradient (DDPG) algorithm was developed. Initially, communication within the network begins with generating a sequence of information bits that represent a specific message acquired from a device. The message is converted to a binary representation using American Standard Code for Information Interchange (ASCII) values, resulting in a binary matrix. Multi-kernel polar encoding is used to construct a generator matrix that supports flexible codeword lengths. Frozen bits are inserted at predefined positions to improve reliability. After encoding, the message results are mapped to Binary Phase Shift Keying (BPSK) modulation, which encodes binary 0 and 1 s using specific phase shifts of a carrier wave. The modulated symbols are then transmitted over Additive White Gaussian Noise (AWGN) channels, which simulate real-world communication conditions by adding random Gaussian noise to the signals. After the signal is transmitted over the channel, reinforcement learning-based SC decoding is applied using the DDPG algorithm. It dynamically adjusts decision thresholds using Log-Likelihood Ratios (LLRs) to minimize latency and reconstruct the original bits. The results show 98.50% accuracy, 92.60% NPV, 92.60% F1-score, and 6.70% FDR. The proposed approach improves transmission by converting information bits into a robust format and reconstructing them accurately despite noise interference. This ensures higher decoding precision and minimizes errors for reliable communication.

DOI
10.1142/s1469026826500288

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Multi-Kernel Polar Codes (MKPCs) play a crucial role in extending the flexibility of polar code construction. Combining different kernel matrices enables a wider range of block lengths and greater adaptability to various communication scenarios while preserving the polarization effect. However, polar codes often suffer from limited scalability and poor error-rate performance at short block lengths, which affects their decoding performance. To overcome these drawbacks, a Successive Cancellation (SC) decoder based on the Deep Deterministic Policy Gradient (DDPG) algorithm was developed. Initially, communication within the network begins with generating a sequence of information bits that represent a specific message acquired from a device. The message is converted to a binary representation using American Standard Code for Information Interchange (ASCII) values, resulting in a binary matrix. Multi-kernel polar encoding is used to construct a generator matrix that supports flexible codeword lengths. Frozen bits are inserted at predefined positions to improve reliability. After encoding, the message results are mapped to Binary Phase Shift Keying (BPSK) modulation, which encodes binary 0 and 1 s using specific phase shifts of a carrier wave. The modulated symbols are then transmitted over Additive White Gaussian Noise (AWGN) channels, which simulate real-world communication conditions by adding random Gaussian noise to the signals. After the signal is transmitted over the channel, reinforcement learning-based SC decoding is applied using the DDPG algorithm. It dynamically adjusts decision thresholds using Log-Likelihood Ratios (LLRs) to minimize latency and reconstruct the original bits. The results show 98.50% accuracy, 92.60% NPV, 92.60% F1-score, and 6.70% FDR. The proposed approach improves transmission by converting information bits into a robust format and reconstructing them accurately despite noise interference. This ensures higher decoding precision and minimizes errors for reliable communication.
With the continuous evolution of 5G communication technology to B5G and the next generation of communication technology, Deep Learning technology will also lead the automation and intelligent transformation of communication systems. Existing research has shown that the combination of deep learning and communication technology is expected to break some performance bottlenecks of traditional communication algorithms and solutions. This paper explores the application of deep learning (DL) in polar decoding algorithms, proposing a DL-aided-FSC (DL-FSC) polar code decoder algorithm. For the DL-FSC decoding algorithm, the conventional successive cancellation (SC) decoder is partitioned into multiple sub-blocks, which are replaced by R0 nodes, R1 nodes and sub-DL decoder. The log-likelihood ratio (LLR) and frozen bit pattern are input to the sub-DL decoder to predict decode codewords under any decoding code rate. Through simulation verification, under the PBCH channel of 5G communication, the DL-FSC decoder achieves similar block error rate (BLER) performance to the SC decoder, even improving by about 1%. In order to verify the performance optimization effect of the proposed algorithm at the hardware level, the DL-FSC deocder circuit design was completed. Through FPGA synthesis, the proposed decoder achieves a throughput of about 4571 Mbps, which is 1.71× improvement in decoding throughput at the expense of increased logic resources.
Non-binary polar codes (NBPCs) decoded by successive cancellation (SC) algorithm have remarkable bit-error-rate performance compared to the binary polar codes (BPCs). Due to its serial nature, SC decoding suffers from long latency. The latency issue in BPCs has been the topic of extensive research and it has been notably resolved by the introduction of fast SC-based decoders. However, the latency problem of NBPCs is mainly untouched and the vast majority of research on NBPCs is devoted to issues concerning design and efficient implementation. In this paper, we propose fast SC decoding for NBPCs constructed based on2×22\times 22×2kernels. In particular, we extend the special nodes of BPCs to their non-binary counterpart and define various non-binary special nodes in the SC decoding tree of NBPCs and propose their fast decoding. This way, we avoid traversing the full decoding tree and significantly reduce the decoding delay compared to symbol-by-symbol SC decoding. We also propose a simplified NBPC structure that facilitates the procedure of non-binary fast SC decoding. Using our proposed fast non-binary decoder, we observe an improvement of more than 96% in latency concerning the original SC decoding. This is while our proposed fast SC decoder for NBPCs incurs no error-rate loss.
For polar codes, perturbing received information can enhance the error-correction performance of successive cancellation (SC) decoding. This is an effective approach for realizing low-latency yet high decoding performance for long polar codes, since each perturbation-enhanced SC (PSC) decoding can be performed in parallel. This paper provides theoretical insights into the soft information perturbation. It first reveals that the PSC decoding can be equivalently viewed as perturbing the SC decoding a posteriori log-likelihood ratio (LLR) of the information bits. Such a revelation enables us to reduce the perturbation complexity by only targeting the information bits, resulting in an improved PSC (IPSC) decoding. By better utilizing the a posteriori LLRs, a set of possibly erroneous estimations can be formed to be perturbed, further reducing the perturbation complexity. Our simulation results show that, for various codeword lengths, the proposed IPSC decoding can achieve a similar performance as the PSC decoding, while yielding significant perturbation complexity reduction.
Non-binary polar codes (NBPCs) decoded by successive cancellation (SC) algorithm have remarkable bit-error-rate performance compared to the binary polar codes (BPCs). Due to the serial nature, SC decoding suffers from large latency. The latency issue in BPCs has been the topic of extensive research and it has been notably resolved by the introduction of fast SC-based decoders. However, the vast majority of research on NBPCs is devoted to issues concerning design and efficient implementation. In this paper, we propose fast SC decoding for NBPCs constructed based on 2 x 2 kernels. In particular, we identify various non-binary special nodes in the SC decoding tree of NBPCs and propose their fast decoding. This way, we avoid traversing the full decoding tree and significantly reduce the decoding delay compared to symbol-by-symbol SC decoding. We also propose a simplified NBPC structure that facilitates the procedure of non-binary fast SC decoding. Using our proposed fast non-binary decoder, we observed an improvement of up to 95% in latency concerning the original SC decoding. This is while our proposed fast SC decoder for NBPCs incurs no error-rate loss.
Polar code has been adopted as the control channel coding scheme for the fifth generation (5G), and the performance of short polar codes is receiving intensive attention. The successive cancellation flipping (SC flipping) algorithm suffers a significant performance loss in short block lengths. To address this issue, we propose a double long short-term memory (DLSTM) neural network to locate the first error bit. To enhance the prediction accuracy of the DLSTM network, all frozen bits are clipped in the output layer. Then, Gaussian approximation is applied to measure the channel reliability and rank the flipping set to choose the least reliable position for multi-bit flipping. To be robust under different codewords, padding and masking strategies aid the network architecture to be compatible with multiple block lengths. Numerical results indicate that the error-correction performance of the proposed algorithm is competitive with that of the CA-SCL algorithm. It has better performance than the machine learning-based multi-bit flipping SC (ML-MSCF) decoder and the dynamic SC flipping (DSCF) decoder for short polar codes.
Polar codes have received growing attention in the past decade and have been selected as the coding scheme for the control channel in the fifth generation (5G) wireless communication systems. However, the conventional polar codes have only been constructed by binary (2×22\times 22×2) kernel, which poses block length limitation to powers of 2. To attain more flexible block lengths, multi-kernel polar codes are proposed. In this paper, a combinational architecture for multi-kernel polar codes with high throughput is proposed based on successive cancellation decoding algorithm. The proposed scheme can decode pure-binary, pure-ternary (3×33\times 33×3), and binary-ternary mixed polar codes. The decoder’s architecture is rate-flexible, meaning that a new code rate can be assigned to the decoder at every clock cycle. The proposed architecture is validated by FPGA implementation, and the results reveal that a code of sizeN=81N=81N=81achieves the coded throughput of 1664.5 Mbps. A Python-based polar compiler is also proposed to automatically generate the HDL modules for target decoders. A designer can input the target block length and kernel ordering of a polar code and get the required VHDL files automatically.