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arXiv:2301.10445 · IEEE Transactions on Circuits and Systems I Regular Papers

High-Throughput Rate-Flexible Combinational Decoders for Multi-Kernel Polar Codes

Hossein Rezaei, Nandana Rajatheva, Matti Latva‐aho

Published Sep 15, 2023• 16 citations
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Abstract

Polar codes have received growing attention in the past decade and have been selected as the coding scheme for the control channel in the fifth generation (5G) wireless communication systems. However, the conventional polar codes have only been constructed by binary ($2\times 2$) kernel, which poses block length limitation to powers of 2. To attain more flexible block lengths, multi-kernel polar codes are proposed. In this paper, a combinational architecture for multi-kernel polar codes with high throughput is proposed based on successive cancellation decoding algorithm. The proposed scheme can decode pure-binary, pure-ternary ($3\times 3$), and binary-ternary mixed polar codes. The decoder’s architecture is rate-flexible, meaning that a new code rate can be assigned to the decoder at every clock cycle. The proposed architecture is validated by FPGA implementation, and the results reveal that a code of size$N=81$achieves the coded throughput of 1664.5 Mbps. A Python-based polar compiler is also proposed to automatically generate the HDL modules for target decoders. A designer can input the target block length and kernel ordering of a polar code and get the required VHDL files automatically.

DOI
10.1109/tcsi.2023.3311514

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Polar codes have received growing attention in the past decade and have been selected as the coding scheme for the control channel in the fifth generation (5G) wireless communication systems. However, the conventional polar codes have only been constructed by binary (2×22\times 22×2) kernel, which poses block length limitation to powers of 2. To attain more flexible block lengths, multi-kernel polar codes are proposed. In this paper, a combinational architecture for multi-kernel polar codes with high throughput is proposed based on successive cancellation decoding algorithm. The proposed scheme can decode pure-binary, pure-ternary (3×33\times 33×3), and binary-ternary mixed polar codes. The decoder’s architecture is rate-flexible, meaning that a new code rate can be assigned to the decoder at every clock cycle. The proposed architecture is validated by FPGA implementation, and the results reveal that a code of sizeN=81N=81N=81achieves the coded throughput of 1664.5 Mbps. A Python-based polar compiler is also proposed to automatically generate the HDL modules for target decoders. A designer can input the target block length and kernel ordering of a polar code and get the required VHDL files automatically.
ABSTRACT Polar codes are the error‐correcting codes adopted as the channel code for the control channel in fifth‐generation new radio (5G NR) standards. The polar code constructed using binary kernels is familiar in 5G and restricts the code length to powers of two. As 5G and beyond (B5G) applications demand higher flexibility, the multi‐kernel polar codes are chosen as a viable candidate. This work proposes a multi‐kernel (MK) polar decoder and analyzes the latency, utilization rate, and hardware utilization efficiency. The last stage of the architecture is replaced by a hard decision (HD) node that decodes two bits simultaneously. The proposed method uses a semi‐parallel architecture with fewer processing units to minimize the hardware resources. The processing unit (PU) consists of a binary processing element (PE) and a mixed PE to adapt to the different binary or ternary kernel stages during decoding. The PEs and the HD logic in the last stage are optimized with MUX‐based logic to reduce the critical path delay. The latency and utilization rate improved by 15%–26% compared to conventional architecture as code length varies from to 3888 and achieved a lower bit‐error rate (BER) of at 3.5 dB for . The decoder is synthesized and implemented on a Virtex‐6 FPGA board for a code length of and compared with other decoders. It is observed that the decoder has the advantage of lower look‐up tables (LUTs) and flip‐flops (FFs) with additional random‐access memory (RAM) usage and higher hardware utilization efficiency (HUE) compared to other existing decoders.
This paper proposes an effective field-programmable gate array (FPGA) implementation of a successive-cancellation (SC) decoder for polar codes that have recently attracted attention as error-correcting codes adopted for 5G wireless systems. We focus on effective ways of partitioning the SC decoding procedure into combinational and sequential logic parts. It can be shown that the SC decoder of length N(= N1N2) can be divided into two parts: N1SC decoders of length N2and a single SC decoder of length N1. While the N1decoders in the first part can perform in parallel, the decoding procedure in the second part is performed sequentially, which causes a bottleneck due to a long latency. We present an SC decoder architecture in which the first part is implemented using sequential logic circuits, and the second part is implemented using only combinational logic circuits. The overall latency and clock frequency of the decoder are balanced by the divisor N1of N, and we show that an appropriate choice of N1yields an efficient implementation with a high throughput. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit-length polar code and show that our FPGA decoder can achieve three times higher throughput than the conventional sequential semi-parallel decoder without significantly increasing the hardware resources.
With the continuous evolution of 5G communication technology to B5G and the next generation of communication technology, Deep Learning technology will also lead the automation and intelligent transformation of communication systems. Existing research has shown that the combination of deep learning and communication technology is expected to break some performance bottlenecks of traditional communication algorithms and solutions. This paper explores the application of deep learning (DL) in polar decoding algorithms, proposing a DL-aided-FSC (DL-FSC) polar code decoder algorithm. For the DL-FSC decoding algorithm, the conventional successive cancellation (SC) decoder is partitioned into multiple sub-blocks, which are replaced by R0 nodes, R1 nodes and sub-DL decoder. The log-likelihood ratio (LLR) and frozen bit pattern are input to the sub-DL decoder to predict decode codewords under any decoding code rate. Through simulation verification, under the PBCH channel of 5G communication, the DL-FSC decoder achieves similar block error rate (BLER) performance to the SC decoder, even improving by about 1%. In order to verify the performance optimization effect of the proposed algorithm at the hardware level, the DL-FSC deocder circuit design was completed. Through FPGA synthesis, the proposed decoder achieves a throughput of about 4571 Mbps, which is 1.71× improvement in decoding throughput at the expense of increased logic resources.
Owing to its high parallelism, belief propagation (BP) decoding is highly amenable to high-throughput implementations and thus represents a promising solution for meeting the ultra-high peak data rate of future communication systems. However, for polar codes, the error-correcting performance of BP decoding is far inferior to that of the widely used CRC-aided successive cancellation list (SCL) decoding algorithm. To close the performance gap to SCL, BP list (BPL) decoding expands the exploration of candidate codewords through multiple permuted factor graphs (PFGs). From an implementation perspective, designing a unified and flexible hardware architecture for BPL decoding that supports various PFGs and code configurations presents a big challenge. In this paper, we propose the first hardware implementation of a BPL decoder for polar codes and overcome the implementation challenge by applying a hardware-friendly algorithm that generates flexible permutations on-the-fly. First, we derive the graph selection gain and provide a sequential generation (SG) algorithm to obtain a near-optimal PFG set. We further prove that any permutation can be decomposed into a combination of multiple fixed routings, and we design a low-complexity permutation network to satisfy the decoding schedule. Our BPL decoder not only has a low decoding latency by executing the decoding and permutation generation in parallel, but also supports an arbitrary list size without any area overhead. Experimental results show that, for length-1024 polar codes with a code rate of one-half, our BPL decoder with 32 PFGs has a similar error-correcting performance to SCL with a list size of 4 and achieves a throughput of 25.63 Gbps and an area efficiency of 29.46 Gbps/mm2^{2}2 at SNR=4.0dB, which is 1.82×\times× and 4.33×\times× faster than the state-of-the-art BP flip and SCL decoders,~respectively
Multi-Kernel Polar Codes (MKPCs) play a crucial role in extending the flexibility of polar code construction. Combining different kernel matrices enables a wider range of block lengths and greater adaptability to various communication scenarios while preserving the polarization effect. However, polar codes often suffer from limited scalability and poor error-rate performance at short block lengths, which affects their decoding performance. To overcome these drawbacks, a Successive Cancellation (SC) decoder based on the Deep Deterministic Policy Gradient (DDPG) algorithm was developed. Initially, communication within the network begins with generating a sequence of information bits that represent a specific message acquired from a device. The message is converted to a binary representation using American Standard Code for Information Interchange (ASCII) values, resulting in a binary matrix. Multi-kernel polar encoding is used to construct a generator matrix that supports flexible codeword lengths. Frozen bits are inserted at predefined positions to improve reliability. After encoding, the message results are mapped to Binary Phase Shift Keying (BPSK) modulation, which encodes binary 0 and 1 s using specific phase shifts of a carrier wave. The modulated symbols are then transmitted over Additive White Gaussian Noise (AWGN) channels, which simulate real-world communication conditions by adding random Gaussian noise to the signals. After the signal is transmitted over the channel, reinforcement learning-based SC decoding is applied using the DDPG algorithm. It dynamically adjusts decision thresholds using Log-Likelihood Ratios (LLRs) to minimize latency and reconstruct the original bits. The results show 98.50% accuracy, 92.60% NPV, 92.60% F1-score, and 6.70% FDR. The proposed approach improves transmission by converting information bits into a robust format and reconstructing them accurately despite noise interference. This ensures higher decoding precision and minimizes errors for reliable communication.
Abstract A hardware architecture is presented to decode (N, K) polar codes based on a low‐density parity‐check code‐like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single‐stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short‐to‐intermediate code lengths was implemented using the Virtex‐7 field‐programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast‐simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10−4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity‐check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra‐scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error‐correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.