ABSTRACT Polar codes are the error‐correcting codes adopted as the channel code for the control channel in fifth‐generation new radio (5G NR) standards. The polar code constructed using binary kernels is familiar in 5G and restricts the code length to powers of two. As 5G and beyond (B5G) applications demand higher flexibility, the multi‐kernel polar codes are chosen as a viable candidate. This work proposes a multi‐kernel (MK) polar decoder and analyzes the latency, utilization rate, and hardware utilization efficiency. The last stage of the architecture is replaced by a hard decision (HD) node that decodes two bits simultaneously. The proposed method uses a semi‐parallel architecture with fewer processing units to minimize the hardware resources. The processing unit (PU) consists of a binary processing element (PE) and a mixed PE to adapt to the different binary or ternary kernel stages during decoding. The PEs and the HD logic in the last stage are optimized with MUX‐based logic to reduce the critical path delay. The latency and utilization rate improved by 15%–26% compared to conventional architecture as code length varies from to 3888 and achieved a lower bit‐error rate (BER) of at 3.5 dB for . The decoder is synthesized and implemented on a Virtex‐6 FPGA board for a code length of and compared with other decoders. It is observed that the decoder has the advantage of lower look‐up tables (LUTs) and flip‐flops (FFs) with additional random‐access memory (RAM) usage and higher hardware utilization efficiency (HUE) compared to other existing decoders.
ABSTRACT Polar codes are the error‐correcting codes adopted as the channel code for the control channel in fifth‐generation new radio (5G NR) standards. The polar code constructed using binary kernels is familiar in 5G and restricts the code length to powers of two. As 5G and beyond (B5G) applications demand higher flexibility, the multi‐kernel polar codes are chosen as a viable candidate. This work proposes a multi‐kernel (MK) polar decoder and analyzes the latency, utilization rate, and hardware utilization efficiency. The last stage of the architecture is replaced by a hard decision (HD) node that decodes two bits simultaneously. The proposed method uses a semi‐parallel architecture with fewer processing units to minimize the hardware resources. The processing unit (PU) consists of a binary processing element (PE) and a mixed PE to adapt to the different binary or ternary kernel stages during decoding. The PEs and the HD logic in the last stage are optimized with MUX‐based logic to reduce the critical path delay. The latency and utilization rate improved by 15%–26% compared to conventional architecture as code length varies from to 3888 and achieved a lower bit‐error rate (BER) of at 3.5 dB for . The decoder is synthesized and implemented on a Virtex‐6 FPGA board for a code length of and compared with other decoders. It is observed that the decoder has the advantage of lower look‐up tables (LUTs) and flip‐flops (FFs) with additional random‐access memory (RAM) usage and higher hardware utilization efficiency (HUE) compared to other existing decoders.
Abstract A hardware architecture is presented to decode (N, K) polar codes based on a low‐density parity‐check code‐like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single‐stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short‐to‐intermediate code lengths was implemented using the Virtex‐7 field‐programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast‐simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10−4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity‐check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra‐scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error‐correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.
Polar codes have received growing attention in the past decade and have been selected as the coding scheme for the control channel in the fifth generation (5G) wireless communication systems. However, the conventional polar codes have only been constructed by binary (2×2) kernel, which poses block length limitation to powers of 2. To attain more flexible block lengths, multi-kernel polar codes are proposed. In this paper, a combinational architecture for multi-kernel polar codes with high throughput is proposed based on successive cancellation decoding algorithm. The proposed scheme can decode pure-binary, pure-ternary (3×3), and binary-ternary mixed polar codes. The decoder’s architecture is rate-flexible, meaning that a new code rate can be assigned to the decoder at every clock cycle. The proposed architecture is validated by FPGA implementation, and the results reveal that a code of sizeN=81achieves the coded throughput of 1664.5 Mbps. A Python-based polar compiler is also proposed to automatically generate the HDL modules for target decoders. A designer can input the target block length and kernel ordering of a polar code and get the required VHDL files automatically.
This paper proposes an effective field-programmable gate array (FPGA) implementation of a successive-cancellation (SC) decoder for polar codes that have recently attracted attention as error-correcting codes adopted for 5G wireless systems. We focus on effective ways of partitioning the SC decoding procedure into combinational and sequential logic parts. It can be shown that the SC decoder of length N(= N1N2) can be divided into two parts: N1SC decoders of length N2and a single SC decoder of length N1. While the N1decoders in the first part can perform in parallel, the decoding procedure in the second part is performed sequentially, which causes a bottleneck due to a long latency. We present an SC decoder architecture in which the first part is implemented using sequential logic circuits, and the second part is implemented using only combinational logic circuits. The overall latency and clock frequency of the decoder are balanced by the divisor N1of N, and we show that an appropriate choice of N1yields an efficient implementation with a high throughput. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit-length polar code and show that our FPGA decoder can achieve three times higher throughput than the conventional sequential semi-parallel decoder without significantly increasing the hardware resources.
This thesis presents a comprehensive study on the hardware implementation of 5G polar decoders, focusing on development, operations, and performance optimization. Polar codes, a pivotal forward error correction technique in 5G communication, are analyzed for their error correction capabilities and efficiency. The research delves into various polar decoding algorithms, including Successive Cancellation (SC), Successive Cancellation List (SCL), and Successive Cancellation Stack (SCS) decodings. Each algorithm's implementation nuances are examined, highlighting their computational complexities and error correction performance. The work further explores FPGA-based implementations, detailing architecture designs that optimize resource utilization and processing speed. Specific emphasis is placed on bit and array length optimizations to enhance decoding efficiency. The thesis also includes a performance analysis comparing different decoding strategies, emphasizing their suitability for real-world 5G applications. Experimental results demonstrate the feasibility and advantages of the proposed hardware implementations, particularly in achieving the low latency and high throughput required for 5G applications. The findings suggest that polar decoders can meet the stringent requirements of next-generation wireless communication systems with proper optimization. Finally, we implement and execute a hardware architecture of the basic Successive Cancellation decoder on an FPGA, performing further optimizations to decrease resource usage and increase execution time without affecting the error correction performance.
Abstract Compared with SC decoding, BP decoding with the parallel mechanism has higher throughput and lower latency, which is more suitable for the demand of 5G scene. To further improve its FER performance and reduce the memory overhead, a recurrent neural network-aided bit-flipping BP decoding of polar codes is proposed. Firstly, it uses bit flip to correct the wrong decoded bits during the decoding iteration. And then, the offset min-sum approximation is used to replace multiplication operation. Lastly the improved recurrent neural network architecture is adopted to realize parameter sharing. The simulation shows that the proposed scheme has a better error correction ability with fewer flipping times, and can effectively reduce the computational resource consumption and extra memory overhead of BP decoding.
Polar code decoding is an algorithmic challenge that is highly sensitive to the latency and throughput. It is used in 5G NR control channels and demands good noise decoding perfor- mance. Decoders such as successive cancellation (SC) and its list variant (SCL) achieve good bit error rates (BER) throughout the signal-to-noise ratio (SNR) regimes, but suffer from high latency and challenges in parallel implementation due to their sequential nature. The belief propagation (BP) decoder is an alternative representation of the polar graph, which allows parallel decoding over the whole codeword, but requires multiple iterations to reach acceptable BER. The hardware-friendly min-sum (MS) algorithmic simplification uses cheap instructions instead of expensive transcendental operations for higher throughput and lower latency, but further negatively impacts the noise decoding performance. This thesis considers the normalized variation of min-sum (NMS), which adds trainable scales per edge in the BP graph, applied to the 5G N=128 rate 1/2 polar code. The weights are trained by treating the unrolled 5 iteration BP graph as a neural network, which achieves a better-or- equal noise performance compared to the true BP decoder, a 0.5 dB average improvement over the untrained MS, and a 5x lower BER than true BP at 6 dB SNR, making the performance roughly comparable to SC in high SNR regions. These improvements are implemented as a single optimized GPU kernel with further optimiza- tions for better throughput, and run on an NVIDIA H100 GPU. The final achieved throughput peaks at 181 million codewords per second (11.6 information Gbit/s), which is around 25x the throughput of the XLA-compiled Sionna framework running the same decoder, and around 190x of a 192-thread CPU implementation.