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ETRI Journal

Fully parallel low‐density parity‐check code‐based polar decoder architecture for 5G wireless communications

Dinesh Kumar Devadoss, Ramapackiam Shantha Selva Kumari

Published Sep 1, 2023• 7 citations
Publisher

Abstract

Abstract A hardware architecture is presented to decode (N, K) polar codes based on a low‐density parity‐check code‐like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single‐stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short‐to‐intermediate code lengths was implemented using the Virtex‐7 field‐programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast‐simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10−4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity‐check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra‐scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error‐correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

DOI
10.4218/etrij.2023-0002

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Abstract A hardware architecture is presented to decode (N, K) polar codes based on a low‐density parity‐check code‐like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single‐stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short‐to‐intermediate code lengths was implemented using the Virtex‐7 field‐programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast‐simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10−4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity‐check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra‐scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error‐correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.
ABSTRACT Polar codes are the error‐correcting codes adopted as the channel code for the control channel in fifth‐generation new radio (5G NR) standards. The polar code constructed using binary kernels is familiar in 5G and restricts the code length to powers of two. As 5G and beyond (B5G) applications demand higher flexibility, the multi‐kernel polar codes are chosen as a viable candidate. This work proposes a multi‐kernel (MK) polar decoder and analyzes the latency, utilization rate, and hardware utilization efficiency. The last stage of the architecture is replaced by a hard decision (HD) node that decodes two bits simultaneously. The proposed method uses a semi‐parallel architecture with fewer processing units to minimize the hardware resources. The processing unit (PU) consists of a binary processing element (PE) and a mixed PE to adapt to the different binary or ternary kernel stages during decoding. The PEs and the HD logic in the last stage are optimized with MUX‐based logic to reduce the critical path delay. The latency and utilization rate improved by 15%–26% compared to conventional architecture as code length varies from to 3888 and achieved a lower bit‐error rate (BER) of at 3.5 dB for . The decoder is synthesized and implemented on a Virtex‐6 FPGA board for a code length of and compared with other decoders. It is observed that the decoder has the advantage of lower look‐up tables (LUTs) and flip‐flops (FFs) with additional random‐access memory (RAM) usage and higher hardware utilization efficiency (HUE) compared to other existing decoders.
In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.
This paper proposes an effective field-programmable gate array (FPGA) implementation of a successive-cancellation (SC) decoder for polar codes that have recently attracted attention as error-correcting codes adopted for 5G wireless systems. We focus on effective ways of partitioning the SC decoding procedure into combinational and sequential logic parts. It can be shown that the SC decoder of length N(= N1N2) can be divided into two parts: N1SC decoders of length N2and a single SC decoder of length N1. While the N1decoders in the first part can perform in parallel, the decoding procedure in the second part is performed sequentially, which causes a bottleneck due to a long latency. We present an SC decoder architecture in which the first part is implemented using sequential logic circuits, and the second part is implemented using only combinational logic circuits. The overall latency and clock frequency of the decoder are balanced by the divisor N1of N, and we show that an appropriate choice of N1yields an efficient implementation with a high throughput. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit-length polar code and show that our FPGA decoder can achieve three times higher throughput than the conventional sequential semi-parallel decoder without significantly increasing the hardware resources.
Abstract This paper presents an intelligent decoding methodology for low-density parity-check (LDPC) and Polar codes (P-C) based on deep reinforcement learning (DRL+Soft) for modern 5G and emerging 6G communication systems. The proposed decoder adapts its decoding strategy in real-time, optimizing bit error rate (BER) performance under varying channel conditions. Evaluation is formulated through performance metrics including BER convergence, reward dynamics, computational complexity (FLOPs), and inference latency. Simulation results show that the DRL+Soft decoder achieves up to a 2.5-fold reduction in computational cost and decreases inference time from 4.8 ms (BP) to 1.6 ms per data block, while maintaining superior BER compared to classical belief propagation (BP) and cyclic redundancy check-aided successive cancellation list (CA-SCL) decoders. The decoder exhibits improved robustness against unpredictable interference and channel impairments, making it suitable for dense device deployments and ultra-reliable low-latency communication (URLLC) scenarios. The methodology also supports reprogramming or retraining of DRL agents without hardware changes, ensuring long-term adaptability for evolving 6G networks. These results demonstrate both theoretical novelty and practical value, providing a scalable and energy-efficient solution for future wireless communication systems.
In the case of short code, polar code demonstrates superior performance compared with Low Density Parity Check (LDPC) code. Particularly in low coding rate scenario, the complexity of Polar code encoding and decoding is significantly lower than that of LDPC code. The technological advantage of Polar code makes it of great value in special application scenarios such as satellite communication and ocean communication. The polar coding scheme can significantly improve the transmission reliability of the communication system, because the satellite spread spectrum communication system generally adopts short code design.In the research of decoding algorithm, the original Serial Cancellation (SC) decoding algorithm has simple rules, but the decoding effect is not ideal under the limited code length, and the serial decoding mechanism leads to large decoding delay. The Successive Cancellation List (SCL) decoding algorithm improves decoding performance by increasing the number of decoding search path. However, maintaining multiple decoding paths can multiply the decoding complexity. Fast node-based decoding algorithm aims to accelerate decoding and reduce latency by defining and simplifying the decoding process for specific nodes, yet they do not optimize the decoding paths. In view of the above problems, this paper proposes a Simplified Parity Check-based Cyclic Redundancy Check (CRC)-Aided Successive Cancellation List (S-PC-CASCL) decoding algorithm. Simulation results demonstrate that the proposed S-PC-CASCL maintains excellent error correction performance while reducing the average list size by up to 16 % under low Signal Noise Ratio (SNR) conditions, thereby lowering computational complexity and decoding latency compared with other widely used polar decoding methods.
This paper presents an efficient hardware architecture of the Check Node (CN) units for the fifth generation (5G) new-radio Low-Density Parity-Check (LDPC) decoders. The proposed CN architecture is designed by splitting the high-degree CN operations into several phases and simplifying computing circuitry and connection wires. The critical path is shortened while the latency increment for one decoding iteration is negligible. Also, the proposed architecture allows to apply adaptively different offset factors when decoding different CN degree. This technique enhances the error rate and performance of our quantized LDPC decoder. The ASIC synthesis results confirm the advantages of the proposed architecture. This later helps reduce the decoder complexity by up to 30% while the operating frequency is enhanced by 10% compared to the conventional solution.