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Fast Node Polar Decoding Method Based on Hybrid Parity Check and CRC

Zongmiao He, Yangjun Chen, Shipeng Gao, Cenyu Pei, Weijie Xia, Xiang Gui Ling

Published Jan 1, 2025• 0 citations

Abstract

In the case of short code, polar code demonstrates superior performance compared with Low Density Parity Check (LDPC) code. Particularly in low coding rate scenario, the complexity of Polar code encoding and decoding is significantly lower than that of LDPC code. The technological advantage of Polar code makes it of great value in special application scenarios such as satellite communication and ocean communication. The polar coding scheme can significantly improve the transmission reliability of the communication system, because the satellite spread spectrum communication system generally adopts short code design.In the research of decoding algorithm, the original Serial Cancellation (SC) decoding algorithm has simple rules, but the decoding effect is not ideal under the limited code length, and the serial decoding mechanism leads to large decoding delay. The Successive Cancellation List (SCL) decoding algorithm improves decoding performance by increasing the number of decoding search path. However, maintaining multiple decoding paths can multiply the decoding complexity. Fast node-based decoding algorithm aims to accelerate decoding and reduce latency by defining and simplifying the decoding process for specific nodes, yet they do not optimize the decoding paths. In view of the above problems, this paper proposes a Simplified Parity Check-based Cyclic Redundancy Check (CRC)-Aided Successive Cancellation List (S-PC-CASCL) decoding algorithm. Simulation results demonstrate that the proposed S-PC-CASCL maintains excellent error correction performance while reducing the average list size by up to 16 % under low Signal Noise Ratio (SNR) conditions, thereby lowering computational complexity and decoding latency compared with other widely used polar decoding methods.

DOI: 10.1109/access.2025.3636559

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Due to the ability to provide superior error-correction performance, the successive cancellation list (SCL) algorithm is widely regarded as one of the most promising decoding algorithms for polar codes with short-to-moderate code lengths. However, the application of SCL decoding in low-latency communication scenarios is limited due to its sequential nature. To reduce the decoding latency, developing tailored fast and efficient list decoding algorithms of specific polar constituent codes (special nodes) is a promising solution. Recently, fast list decoding algorithms are proposed by considering special nodes with low code rates. Aiming to further speedup the SCL decoding, this paper presents fast list decoding algorithms for two types of high-rate special nodes, namely single-parity-check (SPC) nodes and sequence rate one or single-parity-check (SR1/SPC) nodes. In particular, we develop two classes of fast list decoding algorithms for these nodes, where the first class uses a sequential decoding procedure to yield decoding latency that is linear with the list size, and the second further parallelizes the decoding process by pre-determining the redundant candidate paths offline. Simulation results show that the proposed list decoding algorithms are able to achieve up to 70.7% lower decoding latency than state-of-the-art fast SCL decoders, while exhibiting the same error-correction performance.

Being able to provide excellent error-correction performance for polar codes with short-to-moderate code length, successive-cancellation list (SCL) is regarded as one of the most promising decoding algorithms. However, the application of SCL decoding in low-latency communication scenarios is limited due to its sequential nature. Recently, fast list decoding algorithms are proposed by considering special nodes with low code rates. Aiming at achieving further speedup for SCL decoding, this paper presents fast list decoding algorithms for two types of high-rate special nodes, namely single-parity-check (SPC) and sequence rate-1(SRI) nodes, based on the minimum-combinations set (MCS) which is able to significantly narrow the search space of candidate paths. Typically, SPC nodes can be directly decoded within one round of path splitting procedure, whereas SR1 nodes, as a group of parallel SPC nodes, can also be decode efficiently. Simulation results show that the proposed fast SCL decoder is able to reduce the decoding latency by 68.4% as compared to the state of the art, without any error-correction performance degradation.

An improved CA-SCL (CRC-Aided Successive Cancellation List) decoding algorithm for Polar codes is proposed in this paper. By introducing the global cyclic redundancy check and local parity check, a lower bit error rate is obtained comparing with the known results. The new algorithm constructs a prune decoding path by the parity check in the local processing. Since the parity check can only detect an odd number of errors, the global CRC is used to increase the error detection ability and the decoding accuracy. The performance of the improved decoding algorithm is better than the known results, especially when the code length is either less than or equal to 512, and the code rate is not greater than 0.5 in case of the signal-to-noise ratio (SNR) higher than 3dB. In particular, when the code length is 256 with code rate of 0.5 and decoding list size of 32 under the condition of bit error rate 10-5on the AWGN channel, the proposed algorithm has around 0.25dB and 0.55dB performance gain comparing with that of the CA-SCL and SCL algorithms, respectively.

By adopting successive cancellation list decoding (SCL), polar codes demonstrate competitive error correction performance over LDPC and Turbo codes. However, SCL decoding suffers from high computational complexity and long decoding latency, especially when the list size is very large. Successive cancellation flip (SCF), as another decoding algorithm that can achieve high error correction performance, has a complexity that is close to that of successive cancellation (SC) decoding. With the observation that SCL and SCF decoding are similar at giving more chances to inspect possible codewords simultaneously or sequentially, a novel hybrid decoder is proposed in this paper, which essentially combines the ideas of SCF and SCL decoders. Moreover, in order to compensate for the degradation of performance caused by the reduction of path splitting and further reduce the decoding latency, the convolutional polar codes are adopted with a designed bit-flipping set. Simulation results demonstrate that the proposed decoder achieves the reduction of decoding latency while attaining better performance than conventional CRC-aided SCL decoder.

Cyclic redundancy check (CRC)-aided successive cancellation list (CA-SCL) decoding algorithm has brought good error performance. Recently, some researchers utilized multiple CRC codes to reduce decoding complexity of CA-SCL decoding algorithm. However, based on CA-SCL decoding frame, we not only reduce decoding complexity but also improve error performance. We divide polar codeword into independent sub-blocks during the process of encoding. Meanwhile, locations of multiple CRC are optimized according to a value of each average Bhattacharyya parameter. Finally, for CA-SCL decoding, results indicate that our constructed polar codes show an admirable error performance and low decoding complexity than that of equal sub-block codewords.

Benefiting from performance advantages under short code lengths, polar codes are well-suited for certain scenarios, such as the future Internet of Things (IoT) applications that require high reliability and low power. Existing list flip decoders can efficiently further enhance the error-correction performance of polar codes with finite code lengths, particularly the dynamic successive cancellation list flip (D-SCLF) decoder with flexible high-order error-correction capability (FHECC). However, to the best of our knowledge, current list flip decoders cannot effectively balance complexity and error-correction efficiency. To address this, we propose a parity-check-aided D-SCLF (PC-DSCLF) decoder. This decoder, based on FHECC and the characteristics of the list flip decoding process, introduces a simplified flip metric and a hybrid check scheme, along with a decoding method that supports the check scheme, enabling it to retain FHECC while achieving low complexity. Simulation results show that the proposed PC-DSCLF decoder achieves up to a 51.1\% average complexity reduction compared to the D-SCLF algorithm with distributed CRC for

PC(512, 256+24)