Abstract Quantum circuit simulators based on the full statevector require O(2n) mem-ory and compute, which caps their reach at roughly twenty-nine qubits on asingle accelerator with eight gigabytes of device memory. This paper presents anative Verilog RTL implementation of an FP64 quantum statevector simulatortargeting the Xilinx Alveo U55C, whose HBM2 subsystem delivers sixteen giga-bytes across independent AXI4 master interfaces at approximately 460 GB/s.The design, called qsim, is a direct, structural translation of a validated HLSkernel (version v06) into hand-written RTL, preserving the numerical modelexactly while enabling explicit control of pipeline structure, memory geometry,and timing closure. The kernel implements nineteen gate opcodes across threespecialised engines: a single-qubit engine (sg engine) executing any 2×2 unitarythrough a pipelined FP64 complex multiplier of seven-cycle latency, a CNOTengine (cnot engine) performing amplitude swaps without arithmetic, and aCZ engine (cz engine) negating amplitudes via IEEE 754 sign-bit inversion. Allthree engines share an eight-port HBM arbiter that maps amplitude indices tobanks by a modulo-eight interleave, the same topology that was validated byrouting on the nine-AXI-master constraint that excluded a prior sixteen-bankdesign from physical implementation. Parametric gate matrices are assembledon-chip from CORDIC-supplied cos and sin values; all other matrices come froma combinational BRAM-free ROM. The system is exposed through a Qiskit 1.0.2BackendV2 whose Python host layer transpiles circuits to the seventeen-gatenative basis, encodes gate packets as 256-bit words, uploads them through theXilinx Runtime, and retrieves the complex128 statevector after kernel comple-tion. RTL simulation with Vivado xsim confirms all eight functional correctnesstests, including Bell state, three-qubit GHZ state, and CZ phase flip. A qubit-sweep experiment running the GHZ circuit from one to twenty qubits showsperfect fidelity (F = 1.0, P (|0⟩) = P (|1⟩) = 0.5 at every amplitude) forn = 1 through n = 15, with execution time scaling at approximately 2.16×per qubit, consistent with the O(n · 2n) cost of n − 1 CNOT gates over 2namplitudes. A same-bank write serialisation defect causes the verification to failfor n ≥ 16 in the testbench; we document, localise, and discuss the fix. Thecomplete RTL design, host driver, and testbench infrastructure are described infull.
Abstract Quantum circuit simulators based on the full statevector require O(2n) mem-ory and compute, which caps their reach at roughly twenty-nine qubits on asingle accelerator with eight gigabytes of device memory. This paper presents anative Verilog RTL implementation of an FP64 quantum statevector simulatortargeting the Xilinx Alveo U55C, whose HBM2 subsystem delivers sixteen giga-bytes across independent AXI4 master interfaces at approximately 460 GB/s.The design, called qsim, is a direct, structural translation of a validated HLSkernel (version v06) into hand-written RTL, preserving the numerical modelexactly while enabling explicit control of pipeline structure, memory geometry,and timing closure. The kernel implements nineteen gate opcodes across threespecialised engines: a single-qubit engine (sg engine) executing any 2×2 unitarythrough a pipelined FP64 complex multiplier of seven-cycle latency, a CNOTengine (cnot engine) performing amplitude swaps without arithmetic, and aCZ engine (cz engine) negating amplitudes via IEEE 754 sign-bit inversion. Allthree engines share an eight-port HBM arbiter that maps amplitude indices tobanks by a modulo-eight interleave, the same topology that was validated byrouting on the nine-AXI-master constraint that excluded a prior sixteen-bankdesign from physical implementation. Parametric gate matrices are assembledon-chip from CORDIC-supplied cos and sin values; all other matrices come froma combinational BRAM-free ROM. The system is exposed through a Qiskit 1.0.2BackendV2 whose Python host layer transpiles circuits to the seventeen-gatenative basis, encodes gate packets as 256-bit words, uploads them through theXilinx Runtime, and retrieves the complex128 statevector after kernel comple-tion. RTL simulation with Vivado xsim confirms all eight functional correctnesstests, including Bell state, three-qubit GHZ state, and CZ phase flip. A qubit-sweep experiment running the GHZ circuit from one to twenty qubits showsperfect fidelity (F = 1.0, P (|0⟩) = P (|1⟩) = 0.5 at every amplitude) forn = 1 through n = 15, with execution time scaling at approximately 2.16×per qubit, consistent with the O(n · 2n) cost of n − 1 CNOT gates over 2namplitudes. A same-bank write serialisation defect causes the verification to failfor n ≥ 16 in the testbench; we document, localise, and discuss the fix. Thecomplete RTL design, host driver, and testbench infrastructure are described infull.
Abstract This paper presents a distributed quantum circuit statevector simulator thatpartitions the full 2n-amplitude state vector across four Xilinx Alveo U55C field-programmable gate arrays, each equipped with eight gigabytes of HBM2. Thearchitecture assigns two top-index qubits as partition bits so that card j ownsall amplitudes whose binary index has bits [n − 2, n − 1] equal to j, givingeach card a local statevector of 2n−2 complex double-precision amplitudes inter-leaved across eight HBM banks under a modulo-eight scheme. Gate executionis divided into three paths: local gates (acting on qubit indices below n − 2)are dispatched directly to the on-card HLS kernel; diagonal gates acting on par-tition qubits (controlled-phase, RZ , phase, CZ) are applied as a scalar phasemultiply without any cross-card data movement; and non-diagonal partition-qubit gates (Hadamard, CNOT) are handled by a three-barrier, double-bufferedshared-memory exchange followed by vectorised host arithmetic. This diagonal-gate local path eliminates cross-card traffic for every controlled-phase gate ina Quantum Fourier Transform, which would otherwise constitute the dominantcommunication bottleneck in a distributed QFT implementation.We validate the system across five quantum algorithm families on real hardware.The Quantum Fourier Transform achieves state fidelity F = 1.000000000000against an independent Qiskit statevector reference for all circuit widths fromn = 4 to n = 18 qubits, with wall-clock times ranging from 0.96 s at fourqubits to 19.1 s at eighteen qubits. Grover search circuits on up to ten qubitsachieve target-state probability exceeding 99.9% in all cases, with measuredfidelity F = 1.0 confirming exact computation on the FPGA hardware. GHZstate preparation, Bell pair generation, QFT–IQFT round-trips, and a nine-qubitShor algorithm component all pass at F = 1.000000000000. At twenty qubits, where each card holds 218 = 262,144 amplitudes consuming four megabytes ofHBM per card, the simulation completes correctly in under two minutes.Compared with the prior single-FPGA 30-qubit statevector engine, the distributed architecture extends the qubit ceiling to 28 qubits (4 GB total HBM)with exact complex128 precision, and removes the routing failure that prevented a sixteen-bank single-kernel design from placing on the XCVU55C. Comparedwith the Matrix Product State engine at 500 qubits, the statevector approachremains exact for arbitrary entanglement, at the cost of exponential memoryscaling rather than polynomial. The companion real-time quantum error correc-tion kernels and the native RTL statevector design together constitutea complete FPGA quantum computing stack, and the multi-FPGA distributedarchitecture presented here occupies the high-fidelity large-scale simulation tierof that stack.
Abstract Statevector simulation of quantum circuits is fundamentally bounded by an expo-nential in the qubit count, which caps single-device simulation at around thirtyqubits regardless of how the arithmetic is laid out in hardware. The matrixproduct state (MPS) representation breaks that ceiling for circuits of boundedentanglement: its memory and time cost grow only linearly in the number ofqubits and polynomially in a single control parameter, the bond dimension χ.This paper presents a quantum circuit simulator built around an MPS engine thatruns its most expensive primitive, the two-site tensor contraction, on a XilinxAlveo U55C FPGA, with the numerically delicate singular value decomposition(SVD) executed by the host. We describe the engine end to end: an eight-bank,modulo-eight interleaved high-bandwidth-memory (HBM) tensor layout that fitswithin a strict nine-AXI-master routing budget; a double-precision HLS contrac-tion kernel that streams complex amplitudes directly from HBM; a co-designsplit that keeps every floating-point divide and square root off the FPGA crit-ical path, motivated by a concrete timing-closure failure we document; a hostbackend that performs SWAP routing, host-side SVD truncation, a bank-alignedallocator, and sequential conditional sampling in O(nχ2) per shot; and a four-card distributed mode that partitions the chain across devices with an O(χ2)boundary-tensor exchange. We then report what the system actually does. Forshallow, low-entanglement circuits the FPGA contraction is a negligible fractionof wall-clock time and classical measurement sampling on the host dominates;we show this directly rather than hiding it. As the bond dimension grows thepicture inverts, and at χ = 64 the FPGA contraction accounts for roughly sev-enty percent of the run, confirming that bond dimension, not qubit count, is theaxis on which this kind of accelerator earns its place. We push circuit width tofive hundred qubits, validate correctness against an independent Qiskit statevector oracle, and include a deliberate falsification experiment: zeroing the kernel output collapses the measured fidelity from above 0.99 to well below the threshold, demonstrating that the FPGA result is load-bearing and not decorative. Weclose with an honest account of the host-sampling bottleneck and the concretekernel and host changes it motivates.
Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with n qubits requires 2n+4 bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.
Classical simulation of quantum circuits remains indispensable for algorithm development, hardware validation, and error analysis in the noisy intermediate-scale quantum (NISQ) era. However, state-vector simulation faces exponential memory scaling, with an n-qubit system requiring O(2^n) complex amplitudes, and existing simulators often lack the flexibility to exploit heterogeneous computing resources at runtime. This paper presents a GPU-accelerated quantum circuit simulation framework that introduces three contributions: (1) an empirical backend selection algorithm that benchmarks CuPy, PyTorch-CUDA, and NumPy-CPU backends at runtime and selects the optimal execution path based on measured throughput; (2) a directed acyclic graph (DAG) based gate fusion engine that reduces circuit depth through automated identification of fusible gate sequences, coupled with adaptive precision switching between complex64 and complex128 representations; and (3) a memory-aware fallback mechanism that monitors GPU memory consumption and gracefully degrades to CPU execution when resources are exhausted. The framework integrates with Qiskit, Cirq, PennyLane, and Amazon Braket through a unified adapter layer. Benchmarks on an NVIDIA A100-SXM4 (40 GiB) GPU demonstrate speedups of 64x to 146x over NumPy CPU execution for state-vector simulation of circuits with 20 to 28 qubits, with speedups exceeding 5x from 16 qubits onward. Hardware validation on an IBM quantum processing unit (QPU) confirms Bell state fidelity of 0.939, a five-qubit Greenberger-Horne-Zeilinger (GHZ) state fidelity of 0.853, and circuit depth reduction from 42 to 14 gates through the fusion pipeline. The system is designed for portability across NVIDIA consumer and data-center GPUs, requiring no vendor-specific compilation steps.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Portability in high-performance quantum-circuit simulation need not begin at the kernel. We present QSimAdv, which makes late binding, rather than a common kernel, the basis of vendor independence. Representation, operator lowering, and data placement are bound only when their required inputs become available. Before full-state allocation, circuit, noise, and output inspection can route eligible generic sampled-count requests to a stabiliser tableau; explicitly requested representations remain fixed. For full-state execution, backend constraints shape fusion; an ordered fused operator binds to a native lowering only after its physical targets are known. A first-class logical-to-physical layout map records non-canonical order across local and rank-address bits, so the dispatcher moves nonlocal targets only on demand. GPU, CPU, and Message Passing Interface (MPI) backends share these semantics while retaining native execution paths. We realize this design on NVIDIA GH200 and AMD MI250X/EPYC systems across local and distributed execution. With matched complex 32-bit floating-point state storage, QSimAdv leads both Aer Hopper configurations at N=32 and Aer's HIP backend at four shared MI250X sizes from N=24 to 30. Strong scaling exposes platform dependence: on setonix, QSimAdv leads both GPU and CPU comparisons at every measured rank, achieving 3.4× and 2.8× speedups, respectively, from one to eight ranks; neither the GH200 path nor the CPU path speeds up at eight ranks. Weak scaling reaches 256 ranks with 2 TiB GPU and 1 TiB CPU states. Together, these results support that portability can reside above the kernel boundary while execution remains native and extends across distributed memory.