Abstract Statevector simulation of quantum circuits is fundamentally bounded by an expo-nential in the qubit count, which caps single-device simulation at around thirtyqubits regardless of how the arithmetic is laid out in hardware. The matrixproduct state (MPS) representation breaks that ceiling for circuits of boundedentanglement: its memory and time cost grow only linearly in the number ofqubits and polynomially in a single control parameter, the bond dimension χ.This paper presents a quantum circuit simulator built around an MPS engine thatruns its most expensive primitive, the two-site tensor contraction, on a XilinxAlveo U55C FPGA, with the numerically delicate singular value decomposition(SVD) executed by the host. We describe the engine end to end: an eight-bank,modulo-eight interleaved high-bandwidth-memory (HBM) tensor layout that fitswithin a strict nine-AXI-master routing budget; a double-precision HLS contrac-tion kernel that streams complex amplitudes directly from HBM; a co-designsplit that keeps every floating-point divide and square root off the FPGA crit-ical path, motivated by a concrete timing-closure failure we document; a hostbackend that performs SWAP routing, host-side SVD truncation, a bank-alignedallocator, and sequential conditional sampling in O(nχ2) per shot; and a four-card distributed mode that partitions the chain across devices with an O(χ2)boundary-tensor exchange. We then report what the system actually does. Forshallow, low-entanglement circuits the FPGA contraction is a negligible fractionof wall-clock time and classical measurement sampling on the host dominates;we show this directly rather than hiding it. As the bond dimension grows thepicture inverts, and at χ = 64 the FPGA contraction accounts for roughly sev-enty percent of the run, confirming that bond dimension, not qubit count, is theaxis on which this kind of accelerator earns its place. We push circuit width tofive hundred qubits, validate correctness against an independent Qiskit statevector oracle, and include a deliberate falsification experiment: zeroing the kernel output collapses the measured fidelity from above 0.99 to well below the threshold, demonstrating that the FPGA result is load-bearing and not decorative. Weclose with an honest account of the host-sampling bottleneck and the concretekernel and host changes it motivates.
Abstract Statevector simulation of quantum circuits is fundamentally bounded by an expo-nential in the qubit count, which caps single-device simulation at around thirtyqubits regardless of how the arithmetic is laid out in hardware. The matrixproduct state (MPS) representation breaks that ceiling for circuits of boundedentanglement: its memory and time cost grow only linearly in the number ofqubits and polynomially in a single control parameter, the bond dimension χ.This paper presents a quantum circuit simulator built around an MPS engine thatruns its most expensive primitive, the two-site tensor contraction, on a XilinxAlveo U55C FPGA, with the numerically delicate singular value decomposition(SVD) executed by the host. We describe the engine end to end: an eight-bank,modulo-eight interleaved high-bandwidth-memory (HBM) tensor layout that fitswithin a strict nine-AXI-master routing budget; a double-precision HLS contrac-tion kernel that streams complex amplitudes directly from HBM; a co-designsplit that keeps every floating-point divide and square root off the FPGA crit-ical path, motivated by a concrete timing-closure failure we document; a hostbackend that performs SWAP routing, host-side SVD truncation, a bank-alignedallocator, and sequential conditional sampling in O(nχ2) per shot; and a four-card distributed mode that partitions the chain across devices with an O(χ2)boundary-tensor exchange. We then report what the system actually does. Forshallow, low-entanglement circuits the FPGA contraction is a negligible fractionof wall-clock time and classical measurement sampling on the host dominates;we show this directly rather than hiding it. As the bond dimension grows thepicture inverts, and at χ = 64 the FPGA contraction accounts for roughly sev-enty percent of the run, confirming that bond dimension, not qubit count, is theaxis on which this kind of accelerator earns its place. We push circuit width tofive hundred qubits, validate correctness against an independent Qiskit statevector oracle, and include a deliberate falsification experiment: zeroing the kernel output collapses the measured fidelity from above 0.99 to well below the threshold, demonstrating that the FPGA result is load-bearing and not decorative. Weclose with an honest account of the host-sampling bottleneck and the concretekernel and host changes it motivates.
Abstract This paper presents a distributed quantum circuit statevector simulator thatpartitions the full 2n-amplitude state vector across four Xilinx Alveo U55C field-programmable gate arrays, each equipped with eight gigabytes of HBM2. Thearchitecture assigns two top-index qubits as partition bits so that card j ownsall amplitudes whose binary index has bits [n − 2, n − 1] equal to j, givingeach card a local statevector of 2n−2 complex double-precision amplitudes inter-leaved across eight HBM banks under a modulo-eight scheme. Gate executionis divided into three paths: local gates (acting on qubit indices below n − 2)are dispatched directly to the on-card HLS kernel; diagonal gates acting on par-tition qubits (controlled-phase, RZ , phase, CZ) are applied as a scalar phasemultiply without any cross-card data movement; and non-diagonal partition-qubit gates (Hadamard, CNOT) are handled by a three-barrier, double-bufferedshared-memory exchange followed by vectorised host arithmetic. This diagonal-gate local path eliminates cross-card traffic for every controlled-phase gate ina Quantum Fourier Transform, which would otherwise constitute the dominantcommunication bottleneck in a distributed QFT implementation.We validate the system across five quantum algorithm families on real hardware.The Quantum Fourier Transform achieves state fidelity F = 1.000000000000against an independent Qiskit statevector reference for all circuit widths fromn = 4 to n = 18 qubits, with wall-clock times ranging from 0.96 s at fourqubits to 19.1 s at eighteen qubits. Grover search circuits on up to ten qubitsachieve target-state probability exceeding 99.9% in all cases, with measuredfidelity F = 1.0 confirming exact computation on the FPGA hardware. GHZstate preparation, Bell pair generation, QFT–IQFT round-trips, and a nine-qubitShor algorithm component all pass at F = 1.000000000000. At twenty qubits, where each card holds 218 = 262,144 amplitudes consuming four megabytes ofHBM per card, the simulation completes correctly in under two minutes.Compared with the prior single-FPGA 30-qubit statevector engine, the distributed architecture extends the qubit ceiling to 28 qubits (4 GB total HBM)with exact complex128 precision, and removes the routing failure that prevented a sixteen-bank single-kernel design from placing on the XCVU55C. Comparedwith the Matrix Product State engine at 500 qubits, the statevector approachremains exact for arbitrary entanglement, at the cost of exponential memoryscaling rather than polynomial. The companion real-time quantum error correc-tion kernels and the native RTL statevector design together constitutea complete FPGA quantum computing stack, and the multi-FPGA distributedarchitecture presented here occupies the high-fidelity large-scale simulation tierof that stack.
Abstract Quantum circuit simulators based on the full statevector require O(2n) mem-ory and compute, which caps their reach at roughly twenty-nine qubits on asingle accelerator with eight gigabytes of device memory. This paper presents anative Verilog RTL implementation of an FP64 quantum statevector simulatortargeting the Xilinx Alveo U55C, whose HBM2 subsystem delivers sixteen giga-bytes across independent AXI4 master interfaces at approximately 460 GB/s.The design, called qsim, is a direct, structural translation of a validated HLSkernel (version v06) into hand-written RTL, preserving the numerical modelexactly while enabling explicit control of pipeline structure, memory geometry,and timing closure. The kernel implements nineteen gate opcodes across threespecialised engines: a single-qubit engine (sg engine) executing any 2×2 unitarythrough a pipelined FP64 complex multiplier of seven-cycle latency, a CNOTengine (cnot engine) performing amplitude swaps without arithmetic, and aCZ engine (cz engine) negating amplitudes via IEEE 754 sign-bit inversion. Allthree engines share an eight-port HBM arbiter that maps amplitude indices tobanks by a modulo-eight interleave, the same topology that was validated byrouting on the nine-AXI-master constraint that excluded a prior sixteen-bankdesign from physical implementation. Parametric gate matrices are assembledon-chip from CORDIC-supplied cos and sin values; all other matrices come froma combinational BRAM-free ROM. The system is exposed through a Qiskit 1.0.2BackendV2 whose Python host layer transpiles circuits to the seventeen-gatenative basis, encodes gate packets as 256-bit words, uploads them through theXilinx Runtime, and retrieves the complex128 statevector after kernel comple-tion. RTL simulation with Vivado xsim confirms all eight functional correctnesstests, including Bell state, three-qubit GHZ state, and CZ phase flip. A qubit-sweep experiment running the GHZ circuit from one to twenty qubits showsperfect fidelity (F = 1.0, P (|0⟩) = P (|1⟩) = 0.5 at every amplitude) forn = 1 through n = 15, with execution time scaling at approximately 2.16×per qubit, consistent with the O(n · 2n) cost of n − 1 CNOT gates over 2namplitudes. A same-bank write serialisation defect causes the verification to failfor n ≥ 16 in the testbench; we document, localise, and discuss the fix. Thecomplete RTL design, host driver, and testbench infrastructure are described infull.
This work presents a matrix product state (MPS) simulation framework for adaptive non-local observable variational quantum circuits (ANO-VQCs) in image super-resolution (SR) beyond the practical limits of statevector simulation. Runtime benchmarks on a single NVIDIA RTX 4070 GPU show that, under the tested shallow-circuit setting, MPS completes ANO-VQC forward feature extraction for individual inputs up to 16 x 16 pixels (256 qubits), whereas statevector simulation encounters a memory bottleneck at 6 x 6 inputs (36 qubits) and exact tensor-network (Exact TN) contraction becomes computationally impractical beyond 12 x 12 inputs (144 qubits). For a fixed 7 x 7 input (49 qubits), a bond-dimension sweep over depths L = 1 to L = 4 shows that the required MPS bond dimension increases with circuit depth. Using Exact TN contraction as the reference, the bond dimension required for near-exact agreement increases from chi = 2 at L = 1 to chi = 16 at L = 4. Finally, 7 x 7 to 28 x 28 Fashion-MNIST SR training with chi = 16 shows that the shallow L = 1 model achieves the lowest loss, lowest LPIPS, and highest PSNR and SSIM among the tested depths. These results highlight MPS as a scalable and controllable simulation backend for ANO-VQC image SR and as a practical tool for studying large-scale quantum algorithms.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Grover's algorithm is a cornerstone of quantum search algorithm, offering quadratic speedup for unstructured problems. However, limited qubit counts and noise in today's noisy intermediate-scale quantum (NISQ) devices hinder large-scale hardware validation, making efficient classical simulation essential for algorithm development and hardware assessment. We present an iterative Grover simulation framework based on matrix product states (MPS) to efficiently simulate large-scale Grover's algorithm. Within the NVIDIA CUDA-Q environment, we compare iterative and common (non-iterative) Grover's circuits across statevector and MPS backends. On the MPS backend at 29 qubits, the iterative Grover's circuit runs about 15x faster than the common (non-iterative) Grover's circuit, and about 3-4x faster than the statevector backend. In sampling experiments, Grover's circuits demonstrate strong low-shot stability: as the qubit number increases beyond 13, a single-shot measurement still closely mirrors the results from 4,096 shots, indicating reliable estimates with minimal sampling and significant potential to cut measurement costs. Overall, an iterative MPS design delivers speed and scalability for Grover's circuit simulation, enabling practical large-scale implementations.
Grover’s algorithm is a cornerstone of quantum search algorithm, offering quadratic speedup for unstructured problems. However, limited qubit counts and noise in today’s noisy intermediate-scale quantum (NISQ) devices hinder large-scale hardware validation, making efficient classical simulation essential for algorithm development and hardware assessment. We present an iterative Grover simulation framework based on matrix product states (MPS) to efficiently simulate large-scale Grover’s algorithm. Within the NVIDIA CUDA-Q environment, we compare iterative and common (non-iterative) Grover’s circuits across statevector and MPS backends. On the MPS backend at 29 qubits, the iterative Grover’s circuit runs about 15× faster than the common (non-iterative) Grover’s circuit, and about 3-4× faster than the statevector backend. In sampling experiments, Grover’s circuits demonstrate strong low-shot stability: as the qubit number increases beyond 13, a single-shot measurement still closely mirrors the results from 4,096 shots, indicating reliable estimates with minimal sampling and significant potential to cut measurement costs. Overall, an iterative MPS design delivers speed and scalability for Grover’s circuit simulation, enabling practical large-scale implementations.