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Optical Fiber Communication Conference

SimDisQ-Layout: Simulating Circuit Layout for Distributed Quantum Computing

Sen Zhang, Yipei Liu, Brian Mark, Weiwen Jiang, Zebo Yang, Lei Yang

Published Jan 1, 2026• 0 citations
Publisher

Abstract

SimDisQ-Layout is the very first tool to automatically compile a quantum circuit across photonic-connected distributed quantum processors. Its design follows a divide-and-conquer paradigm for circuit partitioning, transpilation, and assembly, producing simulatable and implementable circuit layouts.
DOI
10.1364/ofc.2026.tu3k.5

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An electronic design and evaluation tool for quantum circuit design is presented. It allows easy implementation of quantum algorithms based on the circuit model of quantum computation. The layout of an ideal circuit network can be designed in the logical layer and then automatically get converted into an encoded form closer to the physical layer. The possibility to select and apply the desired quantum error-correcting code enables to study a particular circuit from the aspect of error correction. Various constructions of the same logical network can be designed in order to compare the gate loads of different implementations and encoding or decoding schemas. It is a well structured software tool enabling expansion of other useful functions for realistic studies on quantum computation.
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Distributed quantum circuit simulation enables the execution of large-scale quantum algorithms by partitioning qubits across multiple computational nodes. However, inefficient qubit placement frequently leads to excessive inter-node communication, severely limiting performance and scalability. This work introduces a communication-aware qubit layout optimization framework that systematically minimizes data exchange among nodes while dynamically selecting the optimal number of computational resources. Integrated into the QuCSLO library, our approach supports dynamic node scaling, OpenQASM parsing, and seamless integration with the QuEST simulator. Extensive evaluations on both synthetic benchmarks and real-world QASMBench circuits demonstrate that optimized layouts significantly reduce communication cuts and yield runtime speedups of over 2x compared to identity layouts, particularly in highly entangled circuits. Our results underscore the critical impact of strategic qubit placement on distributed simulation efficiency and provide a practical, resource-scalable solution for quantum workloads.
Due to its effect on the success rate of a quantum circuit, quantum layout synthesis is a crucial step for circuit compilation. As such, having a layout synthesis tool that provides high solution quality is important to maximize circuit performance and fidelity for NISQ application. Previous heuristic approaches have been shown to be far from optimal when evaluated on known-optimal benchmarks. Alternatively, exact layout synthesis tools can generate optimal results with the aid of constraint solvers but generally suffer from scalability issues because of inefficient encodings and slow optimization methods. In this paper, we propose a scalable optimal layout synthesis tool that improves upon previous works, through a more succinct problem formulation as well as better encoding techniques. Additionally, we implement a depth and SWAP count optimization feature that performs iterative refinement under a fixed time budget. Experimental results show that for depth optimization, our tool can achieve a 692× speedup over the state-of-the-art optimal layout synthesis, and for SWAP optimization, we can obtain a 6,957× speedup on average. Compared to a leading heuristic-based synthesizer, for depth optimization, we can solve circuits consisting of 54 program qubits and 1726 gates within 11 hours with an 18× depth reduction and by 12× SWAP count reduction on average.