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arXiv:2511.19791

An End-to-End Distributed Quantum Circuit Simulator

Sen Zhang, Xiong, Lingjun, Y T Liu, Brian L. Mark, Lei Yang, Yang, Zebo, Weiwen Jiang

Published Nov 24, 2025• 0 citations
arXivHTMLPDF

Abstract

Quantum computing has made substantial progress in recent years; however, its scalability remains constrained on a monolithic quantum processing unit (QPU). Distributed quantum computing (DQC) offers a pathway by coordinating multiple QPUs to execute large-scale circuits. Yet, DQC still faces practical barriers, as its realization depends on advances in hardware-level components such as quantum transducers and high-fidelity entanglement-distribution modules. While these technologies continue to improve, mature DQC platforms remain unavailable. In the meantime, researchers need to assess the benefits of DQC and evaluate emerging DQC designs, but the software ecosystem lacks a circuit-level simulator that models heterogeneous backends, noisy connections, and distributed execution. To fill this gap, this paper proposes SimDisQ, the first end-to-end circuit-level DQC simulator, composed of a set of novel DQC-oriented automated simulation toolkits and communication noise models that can interoperate with existing toolkits in mainstream quantum software ecosystems. Leveraging circuit-level simulation capabilities, SimDisQ enables quantitative exploration of architectural design trade-offs, communication fidelity constraints, and new circuit optimization challenges introduced by DQC, providing a foundation for future research in this promising direction. Benchmarking experiments using SimDisQ respond to a couple of open questions in the community; for example, noisy simulation of superconducting and trapped-ion qubits, with a reasonable entanglement-distribution fidelity, reveal that heterogeneous QPUs can indeed yield higher execution fidelity.

DOI
10.48550/arxiv.2511.19791

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Quantum computing has made substantial progress in recent years; however, its scalability remains constrained on a monolithic quantum processing unit (QPU). Distributed quantum computing (DQC) offers a pathway by coordinating multiple QPUs to execute large-scale circuits. Yet, DQC still faces practical barriers, as its realization depends on advances in hardware-level components such as quantum transducers and high-fidelity entanglement-distribution modules. While these technologies continue to improve, mature DQC platforms remain unavailable. In the meantime, researchers need to assess the benefits of DQC and evaluate emerging DQC designs, but the software ecosystem lacks a circuit-level simulator that models heterogeneous backends, noisy connections, and distributed execution. To fill this gap, this paper proposes SimDisQ, the first end-to-end circuit-level DQC simulator, composed of a set of novel DQC-oriented automated simulation toolkits and communication noise models that can interoperate with existing toolkits in mainstream quantum software ecosystems. Leveraging circuit-level simulation capabilities, SimDisQ enables quantitative exploration of architectural design trade-offs, communication fidelity constraints, and new circuit optimization challenges introduced by DQC, providing a foundation for future research in this promising direction. Benchmarking experiments using SimDisQ respond to a couple of open questions in the community; for example, noisy simulation of superconducting and trapped-ion qubits, with a reasonable entanglement-distribution fidelity, reveal that heterogeneous QPUs can indeed yield higher execution fidelity.
Distributed Quantum Computing (DQC) enables scalable quantum execution by interconnecting multiple quantum processing units (QPUs) through quantum networks. In DQC, end-to-end performance is jointly affected by circuit partitioning, entanglement routing, scheduling, and heterogeneous hardware characteristics. However, existing studies often optimize these components independently, providing limited understanding of their cross-layer interactions. In this paper, we present a cross-layer joint-optimization study for DQC using the previously developed SimDisQ-Net simulator. Through simulations, we find that circuit orchestration is one of the dominant factors affecting distributed execution quality, while network-layer mechanisms provide secondary but still meaningful improvements. We further demonstrate that traditional communication metrics, such as hop count or remote-gate count alone, are insufficient predictors of execution quality due to the strong interaction among path fidelity, hardware characteristics, and circuit structure. Motivated by these findings, we propose a topology-aware fidelity proxy (TAFP) evaluation approach that approximates distributed execution fidelity, enabling efficient evaluation of candidate circuit optimizations without time-consuming simulation. Our results highlight the importance of integrated circuit-network orchestration for scalable DQC.
Distributed quantum computing (DQC) connects multiple quantum processing units to overcome the scale limits of monolithic hardware. We introduce SeQUeNCe...DQC a new top-level module within the SeQUeNCe package that compiles monolithic circuits into topology-aware execution plans and coordinates their execution using SeQUeNCe's existing quantum-network modules and protocols. We validate SeQUeNCe...DQC by reproducing a two-node trapped-ion Grover experiment in simulation and comparing success probabilities with the reported 71% benchmark. We then evaluate how compiler strategy, topology, and memory capacity jointly govern distributed circuit execution time and success rate. In these experiments, our hybrid compilers successfully identified mixed TeleGate/TeleData execution plans that outperformed pure gate-teleportation strategies. By capturing the physical overhead of distributed quantum primitives, SeQUeNCe...DQC provides a rigorous platform for co-designing DQC software and hardware architectures.
As distributed quantum computing (DQC) offers a leading path towards scalable quantum computation, the ability to benchmark distributed algorithms under realistic conditions becomes critical for system co-design. However, without access to physical systems, researchers lack tools to evaluate distribution protocols. We introduce Q-DICE (Quantum Distributed Interconnect Compiler and Emulator), a hardware-aware emulation environment for benchmarking distributed quantum circuits on classical simulators and on NISQ-era monolithic hardware. This work provides three core contributions: (1) a programmatic scheme to construct distributed QPU backends, utilizing two novel techniques - QPU slicing and stitching - to facilitate distributed circuit mapping, (2) a methodology for modeling nonlocal link noise using physically motivated Kraus operators and stochastic error channels, and (3) a boundary-aware circuit mapping algorithm enforcing distributed QPU topology constraints during transpilation. Together, these components constitute a distribution-aware compiler and noise-modeling engine that faithfully enforces the physical limitations of distributed quantum hardware within existing execution environments. We validate Q-DICE against a multitude of experimentally demonstrated quantum circuits, including a distributed Grover's search on optically linked trapped-ion hardware, achieving a worst-case fidelity deviation of 4% between simulated and experimental results. These findings demonstrate Q-DICE's capacity to accurately reproduce real distributed quantum system behavior across platforms, streamlining experimentation with distributed quantum algorithms and architectures.
Distributed Quantum Computing (DQC) addresses the physical scaling limitations of monolithic quantum processors by networking modular Quantum Processing Units (QPUs). Efficient execution of quantum algorithms on DQC architectures requires compiling them across QPUs while minimizing inter-QPU communication bottlenecks, primarily through circuit partitioning. However, current evaluations of state-of-the-art partitioning heuristics focus primarily on the total entanglement cost of the partitions, failing to capture the broader structural and temporal overheads introduced by distributed network constraints. This paper addresses this evaluation gap by applying established monolithic benchmarking metrics to partitioned distributed circuits to quantify the performance impact of network constraints. Using an open-source, automated evaluation pipeline, we systematically assess diverse partitioning algorithms across standardized workloads and quantum network topologies. Our empirical results reveal that partitioning algorithms with comparable entanglement costs can still introduce drastically different physical execution penalties. By exposing these hidden trade-offs, such as severe increases in circuit depth and substantial reductions in gate density, this study demonstrates that comprehensive circuit-level metrics are essential for guiding the future design of DQC compilers.
As quantum computers scale, single-chip architectures face inherent limitations in qubit count. This drives the need for modular quantum computing and quantum data centers (QDCs), where multiple quantum processor units (QPUs) are interconnected to enable the distributed execution of a quantum algorithm. However, evaluating distributed quantum computing (DQC) architectures is challenging. Classical simulation is limited by the exponential growth of the state vector, limiting its ability to model large systems and realistically capture hardware noise and timing. Meanwhile, implementing QDC introduces interconnect noise challenges such as transduction inefficiency and optical fiber loss. In this work, we introduce a hardware-based emulation framework by partitioning a single quantum processor’s qubit coupling map into multiple logical QPUs. We show how noise arising from transduction and optical fibers can be modeled by adding an ancilla qubit representing the environment, based on quantum collision dynamics. This model is then translated into a gate-based circuit, in which the couplings between each portion act as controllable noisy quantum communication channels. We demonstrate the framework on IBM quantum hardware by executing remote gates under controllable communication noise. To highlight the flexibility of the platform, we further replicate the implementation results of the distributed Grover’s search algorithm on an ion-trap system. Finally, we test a larger circuit, i.e., a five-qubit quantum Fourier transform (QFT), achieving reasonable fidelity across logical QPUs. Overall, the framework provides a scalable hardware-level emulation platform that captures noise sources through physical qubits and is compatible with any platform supporting the Qiskit SDK.
Scalable quantum computing requires architectural solutions beyond monolithic processors. Distributed quantum computing (DQC) addresses this challenge by interconnecting smaller quantum nodes through quantum communication protocols, enabling collaborative computation. While several experimental and theoretical proposals for DQC exist, emulator platforms are essential tools for exploring their feasibility under realistic conditions. In this work, we introduce a benchmarking framework to evaluate DQC emulators using a distributed implementation of the inverse Quantum Fourier Transform (QFT†\mathrm{QFT}^{\dagger}QFT†) as a representative test case, which enables efficient phase recovery from pre-encoded Fourier states. The QFT is partitioned across nodes using teleportation-based protocols, and performance is analyzed in terms of execution time, memory usage, and fidelity with respect to a monolithic baseline. As part of this work, we review a broad range of emulators, identifying their capabilities and limitations for programming distributed quantum algorithms. Many platforms either lacked support for teleportation protocols or required complex workarounds. Consequently, we select and benchmark four representative emulators: Qiskit Aer, SquidASM, Interlin-q, and SQUANCH. They differ significantly in their support for discrete-event simulation, quantum networking, noise modeling, and parallel execution. Our results highlight the trade-offs between architectural fidelity and simulation scalability, providing a foundation for future emulator development and the validation of distributed quantum protocols. This framework can be extended to support additional algorithms and emulators.