As quantum computers scale, single-chip architectures face inherent limitations in qubit count. This drives the need for modular quantum computing and quantum data centers (QDCs), where multiple quantum processor units (QPUs) are interconnected to enable the distributed execution of a quantum algorithm. However, evaluating distributed quantum computing (DQC) architectures is challenging. Classical simulation is limited by the exponential growth of the state vector, limiting its ability to model large systems and realistically capture hardware noise and timing. Meanwhile, implementing QDC introduces interconnect noise challenges such as transduction inefficiency and optical fiber loss. In this work, we introduce a hardware-based emulation framework by partitioning a single quantum processor’s qubit coupling map into multiple logical QPUs. We show how noise arising from transduction and optical fibers can be modeled by adding an ancilla qubit representing the environment, based on quantum collision dynamics. This model is then translated into a gate-based circuit, in which the couplings between each portion act as controllable noisy quantum communication channels. We demonstrate the framework on IBM quantum hardware by executing remote gates under controllable communication noise. To highlight the flexibility of the platform, we further replicate the implementation results of the distributed Grover’s search algorithm on an ion-trap system. Finally, we test a larger circuit, i.e., a five-qubit quantum Fourier transform (QFT), achieving reasonable fidelity across logical QPUs. Overall, the framework provides a scalable hardware-level emulation platform that captures noise sources through physical qubits and is compatible with any platform supporting the Qiskit SDK.
As quantum computers scale, single-chip architectures face inherent limitations in qubit count. This drives the need for modular quantum computing and quantum data centers (QDCs), where multiple quantum processor units (QPUs) are interconnected to enable the distributed execution of a quantum algorithm. However, evaluating distributed quantum computing (DQC) architectures is challenging. Classical simulation is limited by the exponential growth of the state vector, limiting its ability to model large systems and realistically capture hardware noise and timing. Meanwhile, implementing QDC introduces interconnect noise challenges such as transduction inefficiency and optical fiber loss. In this work, we introduce a hardware-based emulation framework by partitioning a single quantum processor’s qubit coupling map into multiple logical QPUs. We show how noise arising from transduction and optical fibers can be modeled by adding an ancilla qubit representing the environment, based on quantum collision dynamics. This model is then translated into a gate-based circuit, in which the couplings between each portion act as controllable noisy quantum communication channels. We demonstrate the framework on IBM quantum hardware by executing remote gates under controllable communication noise. To highlight the flexibility of the platform, we further replicate the implementation results of the distributed Grover’s search algorithm on an ion-trap system. Finally, we test a larger circuit, i.e., a five-qubit quantum Fourier transform (QFT), achieving reasonable fidelity across logical QPUs. Overall, the framework provides a scalable hardware-level emulation platform that captures noise sources through physical qubits and is compatible with any platform supporting the Qiskit SDK.
Scalable quantum computing requires architectural solutions beyond monolithic processors. Distributed quantum computing (DQC) addresses this challenge by interconnecting smaller quantum nodes through quantum communication protocols, enabling collaborative computation. While several experimental and theoretical proposals for DQC exist, emulator platforms are essential tools for exploring their feasibility under realistic conditions. In this work, we introduce a benchmarking framework to evaluate DQC emulators using a distributed implementation of the inverse Quantum Fourier Transform (QFT†) as a representative test case, which enables efficient phase recovery from pre-encoded Fourier states. The QFT is partitioned across nodes using teleportation-based protocols, and performance is analyzed in terms of execution time, memory usage, and fidelity with respect to a monolithic baseline.
As part of this work, we review a broad range of emulators, identifying their capabilities and limitations for programming distributed quantum algorithms. Many platforms either lacked support for teleportation protocols or required complex workarounds. Consequently, we select and benchmark four representative emulators: Qiskit Aer, SquidASM, Interlin-q, and SQUANCH. They differ significantly in their support for discrete-event simulation, quantum networking, noise modeling, and parallel execution. Our results highlight the trade-offs between architectural fidelity and simulation scalability, providing a foundation for future emulator development and the validation of distributed quantum protocols. This framework can be extended to support additional algorithms and emulators.
As distributed quantum computing (DQC) offers a leading path towards scalable quantum computation, the ability to benchmark distributed algorithms under realistic conditions becomes critical for system co-design. However, without access to physical systems, researchers lack tools to evaluate distribution protocols. We introduce Q-DICE (Quantum Distributed Interconnect Compiler and Emulator), a hardware-aware emulation environment for benchmarking distributed quantum circuits on classical simulators and on NISQ-era monolithic hardware. This work provides three core contributions: (1) a programmatic scheme to construct distributed QPU backends, utilizing two novel techniques - QPU slicing and stitching - to facilitate distributed circuit mapping, (2) a methodology for modeling nonlocal link noise using physically motivated Kraus operators and stochastic error channels, and (3) a boundary-aware circuit mapping algorithm enforcing distributed QPU topology constraints during transpilation. Together, these components constitute a distribution-aware compiler and noise-modeling engine that faithfully enforces the physical limitations of distributed quantum hardware within existing execution environments. We validate Q-DICE against a multitude of experimentally demonstrated quantum circuits, including a distributed Grover's search on optically linked trapped-ion hardware, achieving a worst-case fidelity deviation of 4% between simulated and experimental results. These findings demonstrate Q-DICE's capacity to accurately reproduce real distributed quantum system behavior across platforms, streamlining experimentation with distributed quantum algorithms and architectures.
Quantum computing has made substantial progress in recent years; however, its scalability remains constrained on a monolithic quantum processing unit (QPU). Distributed quantum computing (DQC) offers a pathway by coordinating multiple QPUs to execute large-scale circuits. Yet, DQC still faces practical barriers, as its realization depends on advances in hardware-level components such as quantum transducers and high-fidelity entanglement-distribution modules. While these technologies continue to improve, mature DQC platforms remain unavailable. In the meantime, researchers need to assess the benefits of DQC and evaluate emerging DQC designs, but the software ecosystem lacks a circuit-level simulator that models heterogeneous backends, noisy connections, and distributed execution. To fill this gap, this paper proposes SimDisQ, the first end-to-end circuit-level DQC simulator, composed of a set of novel DQC-oriented automated simulation toolkits and communication noise models that can interoperate with existing toolkits in mainstream quantum software ecosystems. Leveraging circuit-level simulation capabilities, SimDisQ enables quantitative exploration of architectural design trade-offs, communication fidelity constraints, and new circuit optimization challenges introduced by DQC, providing a foundation for future research in this promising direction. Benchmarking experiments using SimDisQ respond to a couple of open questions in the community; for example, noisy simulation of superconducting and trapped-ion qubits, with a reasonable entanglement-distribution fidelity, reveal that heterogeneous QPUs can indeed yield higher execution fidelity.
Distributed quantum computing is a promising way of overcoming the scalability challenges of quantum computers, but establishing quantum links over large distances remains difficult. Therefore, in this thesis, we explore quantum data centres (QDCs), in which multiple quantum processing units (QPUs) are housed together within the same warehouse and linked together over short links. By considering such a setting, we avoid the challenges of long-distance quantum communications while retaining the scalability of distributed architectures. We focus primarily on understanding and quantifying the role of noise in QDCs. We compare the impact of different types of noise in the QDC setting and explore various types of inter-QPU gate. Both individual inter-QPU gates and an assortment of larger distributed quantum circuits are investigated. Based on our findings, we evaluate strategies for the handling of noise, considering both quantum error detection and entanglement distillation based solutions. We also provide a preliminary investigation into the use of QDCs for generating entangled resource states suitable for quantum communications or measurement based quantum computing applications. A major contribution of this thesis is the development of a novel simulation framework for distributed quantum computing, which formed the basis of many of the results obtained. The framework enables users to easily specify distributed quantum circuits or import circuits designed for a single-QPU and convert them to a distributed circuit. Many of the complications of interpreting a distributed quantum circuit, such as the management of communication qubits are also handled automatically. Moreover, the framework's built-in interpreter can interpret common building blocks of distributed quantum computing, such as inter-QPU gates.
Scalable distributed quantum computing (DQC) has motivated the design of multiple quantum data-center (QDC) architectures that overcome the limitations of single quantum processors through modular interconnection. While these architectures adopt fundamentally different design philosophies, their relative performance under realistic quantum hardware constraints remains poorly understood.
In this paper, we present a systematic benchmarking study of four representative QDC architectures-QFly, BCube, Clos, and Fat-Tree-quantifying their impact on distributed quantum circuit execution latency, resource contention, and scalability. Focusing on quantum-specific effects absent from classical data-center evaluations, we analyze how optical-loss-induced Einstein-Podolsky-Rosen (EPR) pair generation delays, coherence-limited entanglement retry windows, and contention from teleportation-based non-local gates shape end-to-end execution performance. Across diverse circuit workloads, we evaluate how architectural properties such as path diversity and path length, and shared BSM (Bell State Measurement) resources interact with optical-switch insertion loss and reconfiguration delay. Our results show that distributed quantum performance is jointly shaped by topology, scheduling policies, and physical-layer parameters, and that these factors interact in nontrivial ways. Together, these insights provide quantitative guidance for the design of scalable and high-performance quantum data-center architectures for DQC.
Scaling quantum computers, i.e., quantum processing units (QPUs) to enable the execution of large quantum circuits is a major challenge, especially for applications that should provide a quantum advantage over classical algorithms. One approach to scale QPUs is to connect multiple machines through quantum and classical channels to form clusters or even quantum networks. Using this paradigm, several smaller QPUs can collectively execute circuits that each would not be able on its own. However, communication between QPUs is costly as it requires generating and maintaining entanglement, and hence it should be used wisely. In this paper, we evaluate the architectures, and in particular the entanglement patterns, of variational quantum circuits in a distributed quantum computing (DQC) setting. That is, using Qiskit, we simulate the execution of an eight qubit circuit using four QPUs each with two computational and two communication qubits where non-local CX-gates are performed using the remote-CX protocol. We compare the performance of various circuits on a binary classification task where training is executed under ideal and testing under noisy conditions. The study provides initial results on suitable VQC architectures for the DQC paradigm, and indicates that a standard VQC baseline is not always the best choice, and alternative architectures that use entanglement between QPUs sparingly deliver better results under noise.