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arXiv:2610.09659

Communication-Aware Qubit Placement and Automatic Node-Count Allocation for Distributed State-Vector Simulation

Íñigo Aréjula-Aísa, Sergio Iserte, Petter Sandås, Ricard S. García-Raigada, Antonio J. Peña

Published Oct 7, 2026• 0 citations
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Abstract

Distributed quantum circuit simulation enables the execution of large-scale quantum algorithms by partitioning qubits across multiple computational nodes. However, inefficient qubit placement frequently leads to excessive inter-node communication, severely limiting performance and scalability. This work introduces a communication-aware qubit layout optimization framework that systematically minimizes data exchange among nodes while dynamically selecting the optimal number of computational resources. Integrated into the QuCSLO library, our approach supports dynamic node scaling, OpenQASM parsing, and seamless integration with the QuEST simulator. Extensive evaluations on both synthetic benchmarks and real-world QASMBench circuits demonstrate that optimized layouts significantly reduce communication cuts and yield runtime speedups of over 2x compared to identity layouts, particularly in highly entangled circuits. Our results underscore the critical impact of strategic qubit placement on distributed simulation efficiency and provide a practical, resource-scalable solution for quantum workloads.

DOI
10.48550/arxiv.2610.09659

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Distributed quantum circuit simulation enables the execution of large-scale quantum algorithms by partitioning qubits across multiple computational nodes. However, inefficient qubit placement frequently leads to excessive inter-node communication, severely limiting performance and scalability. This work introduces a communication-aware qubit layout optimization framework that systematically minimizes data exchange among nodes while dynamically selecting the optimal number of computational resources. Integrated into the QuCSLO library, our approach supports dynamic node scaling, OpenQASM parsing, and seamless integration with the QuEST simulator. Extensive evaluations on both synthetic benchmarks and real-world QASMBench circuits demonstrate that optimized layouts significantly reduce communication cuts and yield runtime speedups of over 2x compared to identity layouts, particularly in highly entangled circuits. Our results underscore the critical impact of strategic qubit placement on distributed simulation efficiency and provide a practical, resource-scalable solution for quantum workloads.
Abstract To overcome the physical limitations of current quantum hardware in terms of available qubits and connectivity, distributed quantum computing (DQC) has emerged as a promising and scalable paradigm. However, in distributed settings, cross-node qubit interactions incur high communication overhead due to the use of costly quantum communication protocols. Efficient circuit partitioning and transmission cost optimization have thus become key challenges. This work addresses the often-overlooked issues of hardware heterogeneity and redundant transmission by proposing a resource-aware partitioning and transmission cost optimization method for distributed quantum circuits. First, we develop a partitioning framework constrained by qubit resources, which accommodates node capacity differences to enable flexible qubit allocation. Second, we model gate dependencies using a directed acyclic graph (DAG) representation and introduce formal criteria to detect “initial-state” and “final-state” redundancies. A measurement-reset strategy is then employed to replace part of the quantum communication, reducing inter-node data transmission. Experimental results on a variety of benchmark circuits and heterogeneous architectures demonstrate that our method significantly reduces transmission cost and improves overall resource utilization. These findings offer both theoretical insight and practical guidance for efficient distributed quantum computing.
Simulating the behavior of quantum circuits on classical computers are one of the widely used approaches for current quantum computing device and quantum algorithm research. State-vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in great memory access and communication overhead far longer than calculation time. Many classical simulators, such as QuEST, are designed by serial execution of quantum gates without using the data locality, and all amplitudes need to be exchanged. Such a gate-unaware full data communication scheme forces powerful computation such as GPUs to spend a lot of time on waiting for data transmission. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. A quantum circuit partition method through gate fusion is first proposed to avoid unnecessary communications. Moreover, a on-demand data communication scheme is proposed to optimize data transfer among computation nodes. Based on these designs, a prototype has been implemented on QuEST. We evaluated on an 8-node cluster with four NVIDIA Tesla V100 GPUs on each node and our designs can achieve 3.0x-15.6x speedup compared to QuEST for 32-34-qubit quantum systems. Moverover, it can scale to simulate 37-qubit quantum system instead of 34-qubit quantum system for QuEST.
Quantum computing offers unparalleled computational capabilities but faces significant challenges, including limited qubit counts, diverse hardware topologies, and dynamic noise and error rates, which hinder scalability and reliability. Distributed quantum computing, particularly chip-to-chip connections, has emerged as a solution by interconnecting multiple processors to collaboratively execute large circuits. While hardware advancements, such as IBM's Quantum Flamingo, focus on improving inter-chip fidelity, limited research addresses efficient circuit cutting and qubit mapping in distributed systems. This project introduces InterPlace, a self-adaptive, hardware-aware framework for chip-to-chip distributed quantum systems. InterPlace analyzes qubit noise and error rates to construct a virtual system topology, guiding circuit partitioning and distributed qubit mapping to minimize SWAP overhead and enhance fidelity. Implemented with IBM Qiskit and compared with the state-of-the-art, InterPlace achieves up to a 53.0\% improvement in fidelity and reduces the combination of on-chip SWAPs and inter-chip operations by as much as 33.3\%, demonstrating scalability and effectiveness in extensive evaluations on real quantum hardware topologies.
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Distributed quantum computation is a promising approach to building a fault-tolerant quantum computer at practical scale. To complete program execution within the minimum time, computational resources and communication resources should be assigned to reduce communication cost. Since remote lattice surgery operation between spatially separated quantum computers takes longer than local lattice surgery, minimizing delay due to the remote lattice surgery is a crucial issue to improve performance of distributed quantum computation. This delay is driven by three related issues: assignment of variable qubits to specific nodes; placement of those qubits within the nodes (resulting in contention for the limited number of local qubit movement paths); and contention for inter-node communication resources (both network interface communication qubits and channels) during concurrent operations. Focusing on the second problem, we propose placing qubits near the network interface based on their inter-node communication needs to avoid intra-node path collisions. We evaluate execution time of the VBE ripple-carry adder in a2×22 \times 22×2grid topology, comparing our proposed qubit assignment approach to random placement. Our results suggest that the proposed model has the potential to reduce resource contention and to improve total execution time.
Simulating the behavior of quantum circuits on classical computers is one of the widely used approaches for current quantum computing device and quantum algorithm research. State- vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in significant memory access and communication overhead far longer than calculation time. Consequently, data communication time often becomes the primary bottleneck in quantum circuit simulation. Many classical simulators, such as QuEST, are designed to execute quantum gates serially without exploiting data locality, and all amplitudes need to be exchanged. Such a gate-unaware full-data communication scheme forces powerful computation such as GPUs to spend substantial time waiting for data transfers. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. We analyze the on-demand communication process and develop a communication cost model to elucidate the relationship between communication costs and circuit partition. Since greedy circuit partition method can only yield locally optimal solutions, we propose a choice-start-node quantum circuit partition method guided by the communication cost model to further reduce communication overhead in quantum circuit simulation. We evaluate on a 4-node cluster with 2 NVIDIA A100 GPUs on each node and our design achieves 59.32× speedup compared to the gate-unaware full-data communication scheme. Furthermore, compared to the greedy circuit partition method, our partition method can achieve simulation acceleration of 1.79×.