Simulating the behavior of quantum circuits on classical computers is one of the widely used approaches for current quantum computing device and quantum algorithm research. State- vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in significant memory access and communication overhead far longer than calculation time. Consequently, data communication time often becomes the primary bottleneck in quantum circuit simulation. Many classical simulators, such as QuEST, are designed to execute quantum gates serially without exploiting data locality, and all amplitudes need to be exchanged. Such a gate-unaware full-data communication scheme forces powerful computation such as GPUs to spend substantial time waiting for data transfers. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. We analyze the on-demand communication process and develop a communication cost model to elucidate the relationship between communication costs and circuit partition. Since greedy circuit partition method can only yield locally optimal solutions, we propose a choice-start-node quantum circuit partition method guided by the communication cost model to further reduce communication overhead in quantum circuit simulation. We evaluate on a 4-node cluster with 2 NVIDIA A100 GPUs on each node and our design achieves 59.32× speedup compared to the gate-unaware full-data communication scheme. Furthermore, compared to the greedy circuit partition method, our partition method can achieve simulation acceleration of 1.79×.
Simulating the behavior of quantum circuits on classical computers is one of the widely used approaches for current quantum computing device and quantum algorithm research. State- vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in significant memory access and communication overhead far longer than calculation time. Consequently, data communication time often becomes the primary bottleneck in quantum circuit simulation. Many classical simulators, such as QuEST, are designed to execute quantum gates serially without exploiting data locality, and all amplitudes need to be exchanged. Such a gate-unaware full-data communication scheme forces powerful computation such as GPUs to spend substantial time waiting for data transfers. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. We analyze the on-demand communication process and develop a communication cost model to elucidate the relationship between communication costs and circuit partition. Since greedy circuit partition method can only yield locally optimal solutions, we propose a choice-start-node quantum circuit partition method guided by the communication cost model to further reduce communication overhead in quantum circuit simulation. We evaluate on a 4-node cluster with 2 NVIDIA A100 GPUs on each node and our design achieves 59.32× speedup compared to the gate-unaware full-data communication scheme. Furthermore, compared to the greedy circuit partition method, our partition method can achieve simulation acceleration of 1.79×.
Simulating the behavior of quantum circuits on classical computers are one of the widely used approaches for current quantum computing device and quantum algorithm research. State-vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in great memory access and communication overhead far longer than calculation time. Many classical simulators, such as QuEST, are designed by serial execution of quantum gates without using the data locality, and all amplitudes need to be exchanged. Such a gate-unaware full data communication scheme forces powerful computation such as GPUs to spend a lot of time on waiting for data transmission. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. A quantum circuit partition method through gate fusion is first proposed to avoid unnecessary communications. Moreover, a on-demand data communication scheme is proposed to optimize data transfer among computation nodes. Based on these designs, a prototype has been implemented on QuEST. We evaluated on an 8-node cluster with four NVIDIA Tesla V100 GPUs on each node and our designs can achieve 3.0x-15.6x speedup compared to QuEST for 32-34-qubit quantum systems. Moverover, it can scale to simulate 37-qubit quantum system instead of 34-qubit quantum system for QuEST.
Executing large quantum circuits is not feasible using the currently available NISQ (noisy intermediate-scale quantum) devices. The high costs of using real quantum devices make it further challenging to research and develop quantum algorithms. As a result, performing classical simulations is usually the preferred method for researching and validating large-scale quantum algorithms. However, these simulations require a huge amount of resources, as each additional qubit exponentially increases the computational space required. Distributed Quantum Computing (DQC) is a promising alternative to reduce the resources required for simulating large quantum algorithms at the cost of increased runtime. This study presents a comparative analysis of two simulation methods: circuit-splitting and full-circuit execution using distributed memory, each having a different type of overhead. The first method, using CutQC, cuts the circuit into smaller subcircuits and allows us to simulate a large quantum circuit on smaller machines. The second method, using Qiskit-Aer-GPU, distributes the computational space across a distributed memory system to simulate the entire quantum circuit. Results indicate that full-circuit executions are faster than circuit-splitting for simulations performed on a single node. However, circuit-splitting simulations show promising results in specific scenarios as the number of qubits is scaled.
Executing large quantum circuits is not feasible using the currently available NISQ (noisy intermediate-scale quantum) devices. The high costs of using real quantum devices make it further challenging to research and develop quantum algorithms. As a result, performing classical simulations is usually the preferred method for researching and validating large-scale quantum algorithms. However, these simulations require a huge amount of resources, as each additional qubit exponentially increases the computational space required. Distributed Quantum Computing (DQC) is a promising alternative to reduce the resources required for simulating large quantum algorithms at the cost of increased runtime. This study presents a comparative analysis of two simulation methods: circuit-splitting and full-circuit execution using distributed memory, each having a different type of overhead. The first method, using CutQC, cuts the circuit into smaller subcircuits and allows us to simulate a large quantum circuit on smaller machines. The second method, using Qiskit-Aer-GPU, distributes the computational space across a distributed memory system to simulate the entire quantum circuit. Results indicate that full-circuit executions are faster than circuit-splitting for simulations performed on a single node. However, circuit-splitting simulations show promising results in specific scenarios as the number of qubits is scaled.
Quantum circuit simulation is essential for researchers to develop and evaluate novel quantum algorithms with classical computers. Although full-state quantum circuit simulations are widely utilized for prototyping and debugging, they are computationally intensive due to the exponential growth in simulation time as the system size grows. To address the performance bottlenecks associated with conventional gate-by-gate simulation, this work refines the block-by-block simulation paradigm through blocking optimization, taking into account the architectural characteristics of hardware. The primary contribution of this research is the gate block search algorithm (GBSA), which efficiently groups the maximum number of quantum gates into gate blocks. This grouping technique enhances data reuse and reduces redundant memory accesses and I/O overhead during gate application. The proposed method is evaluated using both gate-level and circuit-level benchmarks on an AMD 64-core processor. Compared to conventional gate-by-gate simulators, such as QuEST and AerSimulator, the proposed approach achieves up to a 4.7× speedup in CPU execution and a 2.9× speedup in SSD-based scenarios. Furthermore, it can lead to a remarkable 46× reduction in memory and I/O traffic. These results indicate that the proposed block-based simulation strategy substantially improves the efficiency of quantum circuit simulation and can be readily adapted to multi-device environments, thereby supporting the rapid development of next-generation quantum algorithms.
Large quantum circuits cannot be executed efectively on available NISQ (noisy intermediatescale quantum) devices.Moreover, due to the associated cost, researching and developing quantum algorithms on real quantum devices is not feasible.Classical simulations are, therefore, the best method to research and validate large-scale quantum algorithms.This, however, requires a large amount of resources as each additional qubit doubles the computational space for a quantum algorithm.Distributed Quantum Computing (DQC) is a promising alternative to reduce the resources required to simulate large quantum algorithms at the cost of increased runtime.This study performs a comparative analysis between two simulation methods, i.e. circuitsplitting versus full-circuit execution using distributed memory, with each method having a diferent type of overhead.The frst approach cuts the circuits into smaller subcircuits and allows us to simulate large quantum circuits using smaller machines.The second approach distributes the computational space across a distributed memory space and simulates the entire circuit.Results show that full-circuit executions are faster than circuit-splitting for simulations executed on a single node.However, circuit-splitting simulations show promising results in specifc scenarios as the number of qubits is scaled.v
The classical simulation of quantum algorithms is a crucial tool for circuit development, testing, and validation. Although acceleration using GPUs significantly reduces simulation time, most high-performance simulators rely on vendor-specific frameworks that target data-center hardware. To broaden access to quantum simulation, this work proposes a vendor-agnostic approach targeting the integrated GPUs commonly found in consumer-grade laptops. A primary challenge in state-vector simulation is its inherently poor spatial locality, which creates a memory bandwidth bottleneck. Consequently, baseline implementations experience a severe degradation in relative GPU speedup as the number of simulated qubits increases. To address this limitation, we introduce a state partitioning optimization that reorganizes the quantum state vector to maximize the last-level cache locality and minimize costly main memory fetches. We evaluate this strategy using a Quantum Phase Estimation algorithm across diverse architectures from Intel, AMD, and Apple. The experimental results demonstrate that the proposed optimization successfully mitigates performance degradation at larger qubit scales. In particular, for a 28-qubit simulation, the optimization reversed a performance deficit on an Intel Core i5, improving the GPU speedup over the CPU from 0.95x to 1.89x, and increased the Apple M1 Pro speedup from 3.71x to 5.88x. Overall, this approach yields consistent execution time improvements, demonstrating the viability of integrated GPUs for efficient quantum circuit simulation.