Simulating the behavior of quantum circuits on classical computers are one of the widely used approaches for current quantum computing device and quantum algorithm research. State-vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in great memory access and communication overhead far longer than calculation time. Many classical simulators, such as QuEST, are designed by serial execution of quantum gates without using the data locality, and all amplitudes need to be exchanged. Such a gate-unaware full data communication scheme forces powerful computation such as GPUs to spend a lot of time on waiting for data transmission. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. A quantum circuit partition method through gate fusion is first proposed to avoid unnecessary communications. Moreover, a on-demand data communication scheme is proposed to optimize data transfer among computation nodes. Based on these designs, a prototype has been implemented on QuEST. We evaluated on an 8-node cluster with four NVIDIA Tesla V100 GPUs on each node and our designs can achieve 3.0x-15.6x speedup compared to QuEST for 32-34-qubit quantum systems. Moverover, it can scale to simulate 37-qubit quantum system instead of 34-qubit quantum system for QuEST.
Simulating the behavior of quantum circuits on classical computers are one of the widely used approaches for current quantum computing device and quantum algorithm research. State-vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in great memory access and communication overhead far longer than calculation time. Many classical simulators, such as QuEST, are designed by serial execution of quantum gates without using the data locality, and all amplitudes need to be exchanged. Such a gate-unaware full data communication scheme forces powerful computation such as GPUs to spend a lot of time on waiting for data transmission. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. A quantum circuit partition method through gate fusion is first proposed to avoid unnecessary communications. Moreover, a on-demand data communication scheme is proposed to optimize data transfer among computation nodes. Based on these designs, a prototype has been implemented on QuEST. We evaluated on an 8-node cluster with four NVIDIA Tesla V100 GPUs on each node and our designs can achieve 3.0x-15.6x speedup compared to QuEST for 32-34-qubit quantum systems. Moverover, it can scale to simulate 37-qubit quantum system instead of 34-qubit quantum system for QuEST.
Simulating the behavior of quantum circuits on classical computers is one of the widely used approaches for current quantum computing device and quantum algorithm research. State- vector simulators keep all the quantum states in main memory, thus consuming a large amount of memory and resulting in significant memory access and communication overhead far longer than calculation time. Consequently, data communication time often becomes the primary bottleneck in quantum circuit simulation. Many classical simulators, such as QuEST, are designed to execute quantum gates serially without exploiting data locality, and all amplitudes need to be exchanged. Such a gate-unaware full-data communication scheme forces powerful computation such as GPUs to spend substantial time waiting for data transfers. In this paper, we propose a gate-aware on-demand communication quantum simulation framework to optimize communication overhead. We analyze the on-demand communication process and develop a communication cost model to elucidate the relationship between communication costs and circuit partition. Since greedy circuit partition method can only yield locally optimal solutions, we propose a choice-start-node quantum circuit partition method guided by the communication cost model to further reduce communication overhead in quantum circuit simulation. We evaluate on a 4-node cluster with 2 NVIDIA A100 GPUs on each node and our design achieves 59.32× speedup compared to the gate-unaware full-data communication scheme. Furthermore, compared to the greedy circuit partition method, our partition method can achieve simulation acceleration of 1.79×.
Distributed quantum circuit simulation enables the execution of large-scale quantum algorithms by partitioning qubits across multiple computational nodes. However, inefficient qubit placement frequently leads to excessive inter-node communication, severely limiting performance and scalability. This work introduces a communication-aware qubit layout optimization framework that systematically minimizes data exchange among nodes while dynamically selecting the optimal number of computational resources. Integrated into the QuCSLO library, our approach supports dynamic node scaling, OpenQASM parsing, and seamless integration with the QuEST simulator. Extensive evaluations on both synthetic benchmarks and real-world QASMBench circuits demonstrate that optimized layouts significantly reduce communication cuts and yield runtime speedups of over 2x compared to identity layouts, particularly in highly entangled circuits. Our results underscore the critical impact of strategic qubit placement on distributed simulation efficiency and provide a practical, resource-scalable solution for quantum workloads.
The classical simulation of quantum algorithms is a crucial tool for circuit development, testing, and validation. Although acceleration using GPUs significantly reduces simulation time, most high-performance simulators rely on vendor-specific frameworks that target data-center hardware. To broaden access to quantum simulation, this work proposes a vendor-agnostic approach targeting the integrated GPUs commonly found in consumer-grade laptops. A primary challenge in state-vector simulation is its inherently poor spatial locality, which creates a memory bandwidth bottleneck. Consequently, baseline implementations experience a severe degradation in relative GPU speedup as the number of simulated qubits increases. To address this limitation, we introduce a state partitioning optimization that reorganizes the quantum state vector to maximize the last-level cache locality and minimize costly main memory fetches. We evaluate this strategy using a Quantum Phase Estimation algorithm across diverse architectures from Intel, AMD, and Apple. The experimental results demonstrate that the proposed optimization successfully mitigates performance degradation at larger qubit scales. In particular, for a 28-qubit simulation, the optimization reversed a performance deficit on an Intel Core i5, improving the GPU speedup over the CPU from 0.95x to 1.89x, and increased the Apple M1 Pro speedup from 3.71x to 5.88x. Overall, this approach yields consistent execution time improvements, demonstrating the viability of integrated GPUs for efficient quantum circuit simulation.
Quantum circuit simulation is essential for researchers to develop and evaluate novel quantum algorithms with classical computers. Although full-state quantum circuit simulations are widely utilized for prototyping and debugging, they are computationally intensive due to the exponential growth in simulation time as the system size grows. To address the performance bottlenecks associated with conventional gate-by-gate simulation, this work refines the block-by-block simulation paradigm through blocking optimization, taking into account the architectural characteristics of hardware. The primary contribution of this research is the gate block search algorithm (GBSA), which efficiently groups the maximum number of quantum gates into gate blocks. This grouping technique enhances data reuse and reduces redundant memory accesses and I/O overhead during gate application. The proposed method is evaluated using both gate-level and circuit-level benchmarks on an AMD 64-core processor. Compared to conventional gate-by-gate simulators, such as QuEST and AerSimulator, the proposed approach achieves up to a 4.7× speedup in CPU execution and a 2.9× speedup in SSD-based scenarios. Furthermore, it can lead to a remarkable 46× reduction in memory and I/O traffic. These results indicate that the proposed block-based simulation strategy substantially improves the efficiency of quantum circuit simulation and can be readily adapted to multi-device environments, thereby supporting the rapid development of next-generation quantum algorithms.
Quantum circuit simulation is crucial for the development of quantum algorithms, particularly given the high cost and noise limitations of physical quantum hardware. While full-state quantum circuit simulation is commonly employed for prototyping and debugging, it poses challenges because of the exponential increase in simulation time for large quantum systems. In this work, we propose an extensible framework designed to enhance simulation performance by optimizing both data locality and computational efficiency, thereby addressing these challenges. This framework is seamlessly integrated with an optimizer that restructures quantum circuits and a simulator that adjusts execution strategies for various quantum operations. For the newly developed components, merge booster and diagonal detector, the underlying algorithms are inspired by the principles of quantum entanglement and gate fusion, as well as by the limitations identified in existing third-party simulation libraries. The experiments were conducted on eight DGX-H100 workstations, each equipped with eight NVIDIA H100 GPUs, employing both gate-level and circuit-level benchmarks. The results indicate a speedup of up to 160 times for circuit-level benchmarks and an acceleration of up to 34 times for diagonal-heavy gate-level benchmarks compared to existing simulators. The proposed methodologies are anticipated to deliver more robust and faster quantum circuit simulations, thereby fostering the advancement of novel quantum algorithms.
As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale quantum) era, quantum algorithm researchers cannot reliably test their algorithms on real quantum hardware, which is still too limited. Instead, quantum computing simulators on classical computing systems are used. In the quantum circuit model, quantum bits (qubits) are operated on by quantum gates. A quantum circuit is a sequence of such quantum gates operating on some number of qubits. A quantum gate applied to a qubit can be controlled by other qubits in the circuit. This applies the gate only to the states which satisfy the required control qubit state. We particularly target FPGAs as our main simulation platform, as these offer potential energy savings when compared to running simulations on CPUs/GPUs. In this work, we present a memory access pattern to optimise the number of iterations that need to be scheduled to execute a quantum gate such that only the iterations which access the required pairs (determined according to the control qubits imposed on the gate) are scheduled. We show that this approach results in a significant reduction in the time required to simulate a gate for each added control qubit. We also show that this approach benefits the simulation time on FPGAs more than CPUs and GPUs and allows to outperform both CPU and GPU platforms in terms of energy efficiency, which is the main factor for scalability of the simulations.