Quantum computing offers unparalleled computational capabilities but faces significant challenges, including limited qubit counts, diverse hardware topologies, and dynamic noise and error rates, which hinder scalability and reliability. Distributed quantum computing, particularly chip-to-chip connections, has emerged as a solution by interconnecting multiple processors to collaboratively execute large circuits. While hardware advancements, such as IBM's Quantum Flamingo, focus on improving inter-chip fidelity, limited research addresses efficient circuit cutting and qubit mapping in distributed systems. This project introduces InterPlace, a self-adaptive, hardware-aware framework for chip-to-chip distributed quantum systems. InterPlace analyzes qubit noise and error rates to construct a virtual system topology, guiding circuit partitioning and distributed qubit mapping to minimize SWAP overhead and enhance fidelity. Implemented with IBM Qiskit and compared with the state-of-the-art, InterPlace achieves up to a 53.0\% improvement in fidelity and reduces the combination of on-chip SWAPs and inter-chip operations by as much as 33.3\%, demonstrating scalability and effectiveness in extensive evaluations on real quantum hardware topologies.
Quantum computing offers unparalleled computational capabilities but faces significant challenges, including limited qubit counts, diverse hardware topologies, and dynamic noise and error rates, which hinder scalability and reliability. Distributed quantum computing, particularly chip-to-chip connections, has emerged as a solution by interconnecting multiple processors to collaboratively execute large circuits. While hardware advancements, such as IBM's Quantum Flamingo, focus on improving inter-chip fidelity, limited research addresses efficient circuit cutting and qubit mapping in distributed systems. This project introduces InterPlace, a self-adaptive, hardware-aware framework for chip-to-chip distributed quantum systems. InterPlace analyzes qubit noise and error rates to construct a virtual system topology, guiding circuit partitioning and distributed qubit mapping to minimize SWAP overhead and enhance fidelity. Implemented with IBM Qiskit and compared with the state-of-the-art, InterPlace achieves up to a 53.0% improvement in fidelity and reduces the combination of on-chip SWAPs and inter-chip operations by as much as 33.3%, demonstrating scalability and effectiveness in extensive evaluations on real quantum hardware topologies.
Quantum computing offers unparalleled computational capabilities but faces significant challenges, including limited qubit counts, diverse hardware topologies, and dynamic noise/error rates, which hinder scalability and reliability. Distributed quantum computing, particularly chip-to-chip connections, has emerged as a solution by interconnecting multiple processors to collaboratively execute large circuits. While hardware advancements, such as IBM's Quantum Flamingo, focus on improving inter-chip fidelity, limited research addresses efficient circuit cutting and qubit mapping in distributed systems. This project introduces DisMap, a self-adaptive, hardware-aware framework for chip-to-chip distributed quantum systems. DisMap analyzes qubit noise and error rates to construct a virtual system topology, guiding circuit partitioning, and distributed qubit mapping to minimize SWAP overhead and enhance fidelity. Implemented with IBM Qiskit and compared with the state-of-the-art, DisMap achieves up to a 20.8\% improvement in fidelity and reduces SWAP overhead by as much as 80.2\%, demonstrating scalability and effectiveness in extensive evaluations on real quantum hardware topologies.
As quantum computing advances toward fault-tolerance through quantum error correction, modular chiplet architectures have emerged to provide the massive qubit counts required while overcoming fabrication limits of monolithic chips. However, this transition introduces a critical compilation gap: existing frameworks cannot handle the scale of fault-tolerant quantum circuits while managing the noisy, sparse interconnects of chiplet backends.
We present Chipmunq, the first hardware-aware compiler for mapping and routing fault-tolerant circuits onto modular architectures. Chipmunq employs a quantum-error-correction-aware partitioning strategy that preserves the integrity of logical qubit patches, preventing prohibitive gate overheads common in general-purpose compilers. Our evaluation demonstrates that Chipmunq achieves a 13.5x speedup in compilation time compared to state-of-the-art tools. By incorporating chiplet constraints and defective qubits, it reduces circuit depth by 86.4% and SWAP gate counts by 91.4% across varying code distances. Crucially, Chipmunq overcomes heterogeneous inter-chiplet links, improving logical error rates by up to two orders of magnitude.
As quantum computing transitions into the Noisy Intermediate-Scale Quantum (NISQ) era, scaling monolithic quantum processors remains a significant challenge due to decoherence and operational noise. This dissertation proposes enhancing the connectivity of distributed quantum systems as a scalable solution, focusing on three major research tasks: architectural co-design, operation scheduling optimization, and network topology design. First, to address the physical qubit limits of single-chip processors, we investigate the co-design of network topology and logical qubit allocation for Distributed Quantum Computing (DQC). By modeling qubit interaction as a graph partition problem, we propose a joint optimization framework to minimize inter-QPU communication overhead. Our results demonstrate that the proposed linearized formulation, TACO-L, significantly outperforms traditional two-stage methods in executing complex quantum circuits. Second, we address the challenge of maintaining high-fidelity long-distance entanglements through the optimization of Swapping and Purification Schemes (SPS). We prove that in Binary systems, any optimal swapping and purification tree (OSPT) must follow a Restricted SPT (RT) pattern, where purification is integrated at the link level prior to swapping. Furthermore, we introduce the gradient-based GradTree algorithm, which enables an efficient search for low-cost, high-fidelity scheduling in complex noise environments. Finally, this dissertation formulates the first general Topology Design Problem (TDP) for quantum networks, jointly optimizing quantum memory allocation, optical channel deployment, and entanglement scheduling. By analyzing flow-based and path-based formulations, we prove the optimality of the Relaxed Complete Swapping Tree (RCST) in minimizing the expected cost of entanglement distribution. Collectively, these contributions provide a comprehensive theoretical and algorithmic framework for building scalable, cost-effective global quantum internet architectures.
Near-term hardware is constrained by high error rates, small qubit counts, and relatively low output fidelity, making the execution of large, high performance quantum circuits difficult. Circuit partitioning (or circuit cutting) has emerged as a promising approach to circumvent these limitations by decomposing circuits into smaller subcircuits at two-qubit interaction points. However, it remains unclear which classes of circuits benefit the most from partitioning and under what hardware conditions it is most effective. In this work, we evaluate the suitability of quantum circuits for partitioning from three perspectives: improving fidelity, enabling distributed execution, and scaling to larger circuit sizes. Specifically, we compare uncut circuit execution against two circuit partitioning approaches: Qiskit's automatic cut finding technique and a custom performance optimized circuit cutting method. We also measure these across GHZ, QFT, brickwork, and random quantum circuits ranging from 4 to 14 qubits, using mean absolute error of expectation values and overall output fidelity. Our results show that partitioning benefits larger, highly interconnected circuits, with our custom method reducing error by up to 55\% and improve fidelity for GHZ circuits, but degrading performance for brickwork circuits at larger scales.
Distributed quantum circuit simulation enables the execution of large-scale quantum algorithms by partitioning qubits across multiple computational nodes. However, inefficient qubit placement frequently leads to excessive inter-node communication, severely limiting performance and scalability. This work introduces a communication-aware qubit layout optimization framework that systematically minimizes data exchange among nodes while dynamically selecting the optimal number of computational resources. Integrated into the QuCSLO library, our approach supports dynamic node scaling, OpenQASM parsing, and seamless integration with the QuEST simulator. Extensive evaluations on both synthetic benchmarks and real-world QASMBench circuits demonstrate that optimized layouts significantly reduce communication cuts and yield runtime speedups of over 2x compared to identity layouts, particularly in highly entangled circuits. Our results underscore the critical impact of strategic qubit placement on distributed simulation efficiency and provide a practical, resource-scalable solution for quantum workloads.
Abstract: This study investigates photonic-interconnected quantum chiplets as a modular hardware pathway for scalable and networked quantum computing. The central problem is that monolithic quantum processors face compounding constraints in yield, wiring density, cryogenic routing, interconnect loss, calibration complexity and non-local connectivity. Photonic interconnection offers a technically plausible route to divide a large quantum computer into smaller processors while preserving quantum communication across modules through fibre links, photonic switches, optical transduction or integrated photonic interposers. The paper develops an academically rigorous framework that connects quantum-chiplet architecture, photonic integration, quantum error correction, control latency and manufacturability. It uses secondary real-data anchors from recent public demonstrations and a transparent engineering analysis to evaluate whether modular photonic networking can satisfy requirements for distributed logical qubits, entanglement generation and fault-tolerant operation. Results indicate that photonic chiplets can reduce scaling penalties relative to a monolithic wiring strategy when interconnect loss, feed-forward latency and module yield are jointly optimized. The study concludes that photonic-interconnected chiplets are not a minor packaging improvement but a possible architectural transition comparable to the movement from single-die classical processors to heterogeneous chiplet systems. The strongest contribution is a system-level evaluation model that links physical photonic performance with computer-architecture metrics and identifies the practical thresholds that must be met for Nature-level experimental validation. Keywords quantum computing chips, photonic chiplets, modular quantum computing, quantum interconnects, distributed quantum processors, silicon photonics, quantum networking, fault-tolerant quantum computing, optical interposers, quantum error correction, entanglement routing, wafer-scale quantum manufacturing, cryogenic control, quantum architecture, quantum hardware scalability