A new generation of high-performance computing systems is enabled by quantum technology, which offers unprecedented processing speed and energy efficiency. This manuscript investigates the implementation of Reversible Programmable Logic Arrays (RPLAs) on real quantum platforms, emphasizing testability and noise resilience as primary design objectives. We present a novel low-cost RPLA architecture capable of realizing multi-output Exclusive Sum-of-Products (ESOP) functions. An algorithm is used to sort and optimize the ESOP product terms, reducing design complexity while supporting energy-efficient computation through reversible logic. The proposed RPLA demonstrates substantial improvements in key quantum primitives and includes enhanced testability features along with an extensive noise analysis performed on Qiskit quantum computing. The noise evaluation incorporates widely used quantum error models, including bit-flip, amplitude damping, depolarizing, and phase damping, to assess the robustness of the design under realistic operating conditions. Furthermore, a Quantum Equivalent Circuit (QEC) is developed, and a comprehensive testability analysis is conducted using the IBM Quantum Experience (IBM-QE), covering Single Gate Missing (SGM) and Single Control-Point Missing (SCP) faults to ensure robust fault detection. Experimental results obtained from IBM-QE indicate that the proposed RPLA achieves improvements of 34.43% in Gate Count (GT), 54.70% in Garbage Outputs (Gar), and 36.72% in Quantum Cost (QC) compared with existing methods. These enhancements highlight the potential of the proposed architecture for practical, sustainable, and energy-efficient quantum computing applications.
A new generation of high-performance computing systems is enabled by quantum technology, which offers unprecedented processing speed and energy efficiency. This manuscript investigates the implementation of Reversible Programmable Logic Arrays (RPLAs) on real quantum platforms, emphasizing testability and noise resilience as primary design objectives. We present a novel low-cost RPLA architecture capable of realizing multi-output Exclusive Sum-of-Products (ESOP) functions. An algorithm is used to sort and optimize the ESOP product terms, reducing design complexity while supporting energy-efficient computation through reversible logic. The proposed RPLA demonstrates substantial improvements in key quantum primitives and includes enhanced testability features along with an extensive noise analysis performed on Qiskit quantum computing. The noise evaluation incorporates widely used quantum error models, including bit-flip, amplitude damping, depolarizing, and phase damping, to assess the robustness of the design under realistic operating conditions. Furthermore, a Quantum Equivalent Circuit (QEC) is developed, and a comprehensive testability analysis is conducted using the IBM Quantum Experience (IBM-QE), covering Single Gate Missing (SGM) and Single Control-Point Missing (SCP) faults to ensure robust fault detection. Experimental results obtained from IBM-QE indicate that the proposed RPLA achieves improvements of 34.43% in Gate Count (GT), 54.70% in Garbage Outputs (Gar), and 36.72% in Quantum Cost (QC) compared with existing methods. These enhancements highlight the potential of the proposed architecture for practical, sustainable, and energy-efficient quantum computing applications.
Quantum counters are very crucial elements in the design of quantum sequential circuits and quantum control systems. This article details the design, implementation, and noise-aware benchmarking of large-scale quantum counter designs based on the Qiskit framework and IBM Quantum computing platforms. The quantum counter architectures introduced are 2-bit, 3-bit, 4-bit, and 5-bit quantum counters which are developed using reversible quantum gates like Pauli-X, Controlled-NOT (CNOT), Toffoli, and Multi-Controlled X (MCX) gates. Firstly, all the counter architectures were confirmed to be working well in the ideal simulation scenario using the Qiskit Aer simulator where they achieved perfect computational fidelity and produced correct counting sequences. For the assessment of practical performance in the Noisy Intermediate-Scale Quantum (NISQ) environment, several quantum noise models, including bit-flip noise, depolarizing noise, amplitude damping noise, and phase damping noise, were introduced within the experimental framework. The experimental findings indicate that as circuits become more complex, the precision of computations decreases in the presence of real-world noise conditions. Under bit-flip noise, the correct counts noted changed from 846 for the 2-bit counter to 620 for the 5-bit counter. Likewise, depolarizing noise led to a slight decline, whereas amplitude damping noise resulted in the most drastic decrease in performance, dropping the correct counts from 253 in the 2-bit design to merely 33 in the 5-bit design. On the contrary, a phase damping noise showed almost no impact and retained 1024 correct counts across all architectures. The scalability analysis demonstrates that quantum counter architectures based on reversible gates can proficiently work over quite extensive qubit configurations while maintaining functional correctness. Nevertheless, the increase in circuit depth and gate complexity mainly results in susceptibility to decoherence and noise accumulation. This work offers a unified framework for the development and evaluation of large-scale quantum sequential circuits and sheds light on building quantum systems that can be used fault-tolerantly in future quantum computing implementations.
In the recent era, Reversible computing is a growing field having applications in nanotechnology, optical information processing, quantum networks etc.In this paper, the authors show the design of a cost effective reversible programmable logic array using VHDL.It is simulated on Xilinx ISE 8.2i and results are shown.The proposed reversible Programming logic array called RPLA is designed by MUX gate & Feynman gate for 3-inputs, which is able to perform any reversible 3-input logic function or Boolean function.Furthermore the quantized analysis with comparative finding is shown for the realized RPLA against the existing one.The result shows improvement in the quantum cost and total logical calculation in proposed RPLA.
In the recent era, Reversible computing is a growing field having applications in nanotechnology, optical information processing, quantum networks etc. In this paper, the authors show the design of a cost effective reversible programmable logic array using VHDL. It is simulated on Xilinx ISE 8.2i and results are shown. The proposed reversible Programming logic array called RPLA is designed by MUX gate & Feynman gate for 3- inputs, which is able to perform any reversible 3- input logic function or Boolean function. Furthermore the quantized analysis with comparative finding is shown for the realized RPLA against the existing one. The result shows improvement in the quantum cost and total logical calculation in proposed RPLA.
Reversible circuits are one of the most promising technologies for replicating inputs from recorded outputs, and it results in lower power dissipation. All gates such as NAND, AND, OR, NOR etc. are irreversible in nature and consume energy during calculations. Similar to quantum circuits, reversible logic circuitry does not consume energy throughout the calculation cycle. Due to this, reversible circuits can be used for quantum communication and other low-power applications. Registers are one of the most important storage components utilised in a wide range of real-time operations. Using expressions of exclusive-or sum of products (ESOP) and modified Fredkin gates, this work presents a novel way for creating a quantum cost-effective universal register circuit. The designed universal register circuitry for left and right shifts are tested in the Xilinx Vivado simulator to ensure that they are functional and logically correct. The proposed universal registers outperform the standard designs in terms of garbage outputs (GO), quantum cost (QC), gate count (GC), and Ancilla inputs (AI), according to the comparative analysis.
Reversible logic, by enabling computations without loss of information, offers a promising approach to significantly reducing energy dissipation, making it a key technology for low-power and quantum computing systems. Parity-preserving reversible circuits further enhance reliability, enabling fault detection in nanoscale systems. Multiplication, a fundamental operation in computing and signal processing, benefits significantly from efficient reversible designs. However, existing reversible Vedic multipliers often suffer from excessive Quantum Cost (QC), Garbage Outputs (GO), and Constant Inputs (CI). This paper proposes two new 2-bit parity-preserving reversible quantum Vedic multipliers, serving as the foundational block for scalable n-bit multipliers, that are enhanced to reduce quantum metrics without compromising performance. The proposed circuits are simulated using the Quirk tool to test their correct functionality. Comparative analysis shows that the best proposed design outperforms existing architectures on average by 34%, 53%, and 9% in constant inputs, garbage outputs, and quantum cost, respectively, providing a fault-tolerant, cost-efficient, and scalable solution for next-generation quantum computing systems.
Reversible circuits are one of the most promising technologies that allow the reproduction of the inputs from the observed outputs and thus reducing the power dissipation in the form of heat. Many basic and universal logic gates i.e. nand, nor, or, and etc. are irreversible and result in energy consumption during calculations. In the reversible technology, like quantum circuits energy is not consumed during the entire calculation process and these circuits can be used for low-power and quantum communication applications circuits. Counters are considered as one of the most important sequential circuits used in many real-time applications. This paper presents a new approach to design a quantum cost-effective reversible up/down counter circuit using exclusive-or sum of product (ESOP) expressions and TR gates. The proposed counter circuits are simulated in the Xilinx Vivado simulator to verify the functionality of the proposed designs. The comparative study indicates that the proposed counters are superior to the best previous designs in terms of quantum cost (QC) and gate count (GC). Moreover, they are very close to or better than the previously available designs in terms of garbage outputs (GO) and Ancilla inputs (AI).