By exploiting quantum mechanical behavior, quantum computers have the potential to carry out classically hard computations, such as the prime factorization of integers, with disruptive, exponentially better efficiency, yet they struggle with classically simple task like integer addition. Hybrid applications, combining both quantum and classical computations, attempt to take advantage of the strength of both approaches while avoiding their weaknesses. In such applications, the design of the interface between quantum and classical computers deserves attention as a potential performance bottleneck. In this thesis, the design of a modular software stack for hybrid quantum/classical applications that is agnostic to the used quantum technology platform is developed both for high-level application-oriented as well as high-performance low-level use-cases. A hardware description language for quantum circuits derived from the industry standard VHDL language is proposed, and its usage in tightly-coupled hybrid applications, where quantum and classical computations overlap in time, is discussed. To enable low-latency coupling, the proposed hybrid architecture connects quantum computations to hardware implementations of timing critical classical computations and utilizes established hardware/software co-design patterns to interface higher-level classical computations. Experimental evidence of noise effects on state-of-the-art quantum hardware is presented for the case of solving partial differential equations. This supports the conclusion that frequent interaction between short and shallow quantum and classical computations is necessary even for loosely-coupled hybrid applications under these circumstances, strengthening the case for a low-latency, high-bandwidth quantum-classical interface as proposed in this thesis.
By exploiting quantum mechanical behavior, quantum computers have the potential to carry out classically hard computations, such as the prime factorization of integers, with disruptive, exponentially better efficiency, yet they struggle with classically simple task like integer addition. Hybrid applications, combining both quantum and classical computations, attempt to take advantage of the strength of both approaches while avoiding their weaknesses. In such applications, the design of the interface between quantum and classical computers deserves attention as a potential performance bottleneck. In this thesis, the design of a modular software stack for hybrid quantum/classical applications that is agnostic to the used quantum technology platform is developed both for high-level application-oriented as well as high-performance low-level use-cases. A hardware description language for quantum circuits derived from the industry standard VHDL language is proposed, and its usage in tightly-coupled hybrid applications, where quantum and classical computations overlap in time, is discussed. To enable low-latency coupling, the proposed hybrid architecture connects quantum computations to hardware implementations of timing critical classical computations and utilizes established hardware/software co-design patterns to interface higher-level classical computations. Experimental evidence of noise effects on state-of-the-art quantum hardware is presented for the case of solving partial differential equations. This supports the conclusion that frequent interaction between short and shallow quantum and classical computations is necessary even for loosely-coupled hybrid applications under these circumstances, strengthening the case for a low-latency, high-bandwidth quantum-classical interface as proposed in this thesis.
We present the design, development, and application of QHDL, a quantum hardware description language specifically designed for tightly-coupled quantum–classical computing systems. Together with the language design principles, we describe the QHDL compiler, debugger, and co-simulation infrastructure. We showcase the benefits of using a quantum–classical integrated approach in four use cases, requiring close quantum–classical device interaction: Bell’s pair circuit, dynamic delay, Quantum Fourier Transform (QFT), and teleportation. To interface with QHDL, we propose to use synchronous techniques that are commonplace in digital hardware design. We illustrate examples of modelling both loosely-coupled and tightly-coupled quantum circuits that use so-called measurement-in-the-middle by utilizing these techniques in QHDL. For clock-cycle accurate implementations, we propose implementing such modules as programmable hardware blocks using Register-Transfer Level (RTL) or gate-level approaches. These approaches provide the highest coupling performance and are feasible to be implemented in state-of-the-art control systems.
Hybrid quantum-classical algorithms have shown great promise in leveraging the computational potential of quantum systems.However, the efficiency of these algorithms is severely constrained by the limitations of current quantum hardware architectures.These architectures, which typically feature a decoupled design, lack both hardware support for low-latency communication and software support for fine-grained optimization.In this paper, we propose Qtenon, a tightly coupled system for efficient hybrid quantum-classical algorithm acceleration.Qtenon is composed of both hardware part and software part.To enable efficient communication and computation, the hardware part provides a unified memory hierarchy, an efficient quantum controller, as well as a multi-stage processing pipeline.The unified memory hierarchy functions as a communication buffer between host and quantum accelerators, with dedicated data paths and interfaces provided by the quantum controller.The multi-stage pipeline leverages hardware pipelines to fully exploit parallelism.To program hybrid quantum-classical algorithms on the hardware, our software part provides a set of instructions for data communication and computation.The instructions also enable fine-grained synchronization and efficient scheduling for quantum-host interaction.We design Qtenon as a RISC-V extended chip and implement it using Chisel.In evaluation, we achieve up to 14.9× end-to-end speedup compared to state-of-the-art work for hybrid quantum-classical algorithms.
Quantum computing is often treated as an experimental add-on: it is often loosely coupled to classical infrastructure through high-level interpreted languages, cloud-based orchestration and physical measurement hardware. However, future deployments in both high-performance computing (HPC) and embedded environments will demand tighter integration for lower latencies, stronger determinism, and architectural consistency. We propose a vertically integrated quantum systems architecture that treats quantum accelerators as peripheral system components. A central element is the Quantum Abstraction Layer (QAL), introduced at the kernel level of the operating system. This design enables real-time, low-latency, and high-throughput interaction between quantum and classical resources and opens the door for robust scheduling, resource management, and cross-stack optimisation. Kernel-space integration is not merely a technical curiosity—it is a necessity. For HPC, it enables scalable, heterogeneous workloads; for embedded systems, it provides a foundation for future quantum deployments far beyond scripting-based control interfaces. We present early-stage results including a virtual QPU model integrated into a QEMU-based prototype system. The architecture is validated through functional emulation and time-accurate FPGA simulations, enabling realistic evaluation of hybrid system performance and quantum advantage scenarios. Our work lays the groundwork for a system-level co-design methodology tailored for the next generation of quantum-classical computing.
The technology of Quantum Computing (QC) is continuously evolving, as researchers explore new technologies and the public gains access to quantum computers with an increasing number of qubits. In addition, the research community and industry are increasingly interested in the potential use, application, and contribution of QCs to large-scale problems in the real world as a result of this technological enhancement. QCs operations are based on quantum mechanics, and their special properties are mainly exploited to solve computationally intensive problems in polynomial time, problems that are commonly unsolvable, even by High-Performance Computing systems (HPCs) in a feasible time. However, since QCs cannot perform as general-purpose computing machines, alternative computational approaches aiming to boost further their enormous computing abilities are requested, and their combination as an additional computing resource to HPC systems is considered as one of the most promising ones. In the proposed hybrid HPCs, the Quantum Processing Units (QPUs), similar to GPUs and CPUs, target specific problems that, through Quantum Algorithms, can exploit quantum properties like quantum entanglement and superposition to achieve substantial performance gains from the HPC point of view. This interconnection between classical HPC systems and QCs towards the creation of Hybrid Quantum-Classical computing systems is neither straightforward nor standardized while crucial for unlocking the real potential of QCs and achieving real performance improvements. The interconnection between the classical and quantum systems can be performed in the hardware, software (system), or application layer. In this study, a concise overview of the existing architectures for the interconnection interface between HPCs and QCs is provided, focusing mainly on hardware approaches that enable effective hybrid quantum-classical operation.
Quantum computers are often treated as experimental add-ons that are loosely coupled to classical infrastructure through high-level interpreted languages and cloud-like orchestration. However, future deployments in both, high-performance computing (HPC) and embedded environments, will demand tighter integration for lower latencies, stronger determinism, and architectural consistency, as well as to implement error correction and other tasks that require tight quantum-classical interaction as generically as possible. We propose a vertically integrated quantum systems architecture that treats quantum accelerators and processing units as peripheral system components. A central element is the Quantum Abstraction Layer (QAL) at operating system kernel level. It aims at real-time, low-latency, and high-throughput interaction between quantum and classical resources, as well as robust low-level quantum operations scheduling and generic resource management. It can serve as blueprint for orchestration of lowlevel computational components “around” a QPU (and inside a quantum computer), and across different modalities. We present first results towards such an integrated architecture, including a virtual QPU model based on QEMU. The architecture is validated through functional emulation on three base architectures (x86_64, ARM64, and RISC-V), and timingaccurate FPGA-based simulations. This allows for a realistic evaluation of hybrid system performance and quantum advantage scenarios. Our work lays the ground for a system-level co-design methodology tailored for the next generation of quantum-classical computing.
One of the primary focuses in the rapidly changing scenery of quantum computing is one of the most promising methodologies for transgressing the current feat of quantum technologies: a better mix of quantum and classical paradigms of computations.This paper suggests a new hybrid quantum-classical processor architecture that augments the computational speed and enhances efficiency by utilizing powers emanating from the quantum and classical processing units.The architecture proposed in the study incorporates quantum processing units with classical processing units, with CPUs interfaced tightly to support dynamic task allocation with a view toward computational requirements.Hybrid processor design caters to the performance of quantum algorithms that usually involve classical preprocessing and postprocessing, such as the Variational Quantum Eigensolver and Quantum Approximate Optimization Algorithm.These algorithms are essential for any complicated optimization, the simulation of quantum systems, and applications in machine learning.We provide an insightful processor architecture design, understanding the communication protocol details between QPU and CPU, the scheduling mechanism for hybrid tasks, and the optimization techniques employed to minimize data transfer overhead while maximizing computational throughput.A lot of these implementation challenges, like quantum error correction, managing the coherence time, and classical-quantum data conversion, are something that innovations in hardware design and software algorithms can achieve.In this paper, the performance of the hybrid processor is, for the first time, fully benchmarked based on simulation and experimental setups.Resultsshow that this hybrid approach outperforms standalone quantum and classical processors on specific computational tasks by ten times in optimization problems and five times for machine learning.These include case studies showing that for some problems, the processor can solve real-world problems much more efficiently than any existing quantum or classical system.Such case studies include quantum chemistry simulations, cryptographic tasks, and training machine learning models.We turn to the scalability and flexibility of the hybrid processor to extend the horizon of these case studies and to bridge the gap between the current quantum computing capabilities and the race toward fully functional quantum computers.This new hybrid quantum-classical processor architecture makes significant progress in quantum computing by providing a pragmatic, workable solution for harnessing quantum mechanics but using the maturity of classical computing.The results show how to proceed with the research involving the hybrid system and the many potential applications of such systems across optimization, cryptography, and artificial intelligence.This study is significant as it offers a practical approach to overcoming the limitations of current quantum and classical processors, providing a pathway to more efficient and scalable computational solutions.