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Future Generation Computer Systems

Tightly-integrated quantum–classical computing using the QHDL hardware description language

Gilbert Netzer, Pratibha Raghupati Hegde, Ivy Bo Peng, Stefano Markidis

Published Jun 27, 2025• 5 citations
Publisher

Abstract

We present the design, development, and application of QHDL, a quantum hardware description language specifically designed for tightly-coupled quantum–classical computing systems. Together with the language design principles, we describe the QHDL compiler, debugger, and co-simulation infrastructure. We showcase the benefits of using a quantum–classical integrated approach in four use cases, requiring close quantum–classical device interaction: Bell’s pair circuit, dynamic delay, Quantum Fourier Transform (QFT), and teleportation. To interface with QHDL, we propose to use synchronous techniques that are commonplace in digital hardware design. We illustrate examples of modelling both loosely-coupled and tightly-coupled quantum circuits that use so-called measurement-in-the-middle by utilizing these techniques in QHDL. For clock-cycle accurate implementations, we propose implementing such modules as programmable hardware blocks using Register-Transfer Level (RTL) or gate-level approaches. These approaches provide the highest coupling performance and are feasible to be implemented in state-of-the-art control systems.

DOI
10.1016/j.future.2025.107977

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We present the design, development, and application of QHDL, a quantum hardware description language specifically designed for tightly-coupled quantum–classical computing systems. Together with the language design principles, we describe the QHDL compiler, debugger, and co-simulation infrastructure. We showcase the benefits of using a quantum–classical integrated approach in four use cases, requiring close quantum–classical device interaction: Bell’s pair circuit, dynamic delay, Quantum Fourier Transform (QFT), and teleportation. To interface with QHDL, we propose to use synchronous techniques that are commonplace in digital hardware design. We illustrate examples of modelling both loosely-coupled and tightly-coupled quantum circuits that use so-called measurement-in-the-middle by utilizing these techniques in QHDL. For clock-cycle accurate implementations, we propose implementing such modules as programmable hardware blocks using Register-Transfer Level (RTL) or gate-level approaches. These approaches provide the highest coupling performance and are feasible to be implemented in state-of-the-art control systems.
By exploiting quantum mechanical behavior, quantum computers have the potential to carry out classically hard computations, such as the prime factorization of integers, with disruptive, exponentially better efficiency, yet they struggle with classically simple task like integer addition. Hybrid applications, combining both quantum and classical computations, attempt to take advantage of the strength of both approaches while avoiding their weaknesses. In such applications, the design of the interface between quantum and classical computers deserves attention as a potential performance bottleneck. In this thesis, the design of a modular software stack for hybrid quantum/classical applications that is agnostic to the used quantum technology platform is developed both for high-level application-oriented as well as high-performance low-level use-cases. A hardware description language for quantum circuits derived from the industry standard VHDL language is proposed, and its usage in tightly-coupled hybrid applications, where quantum and classical computations overlap in time, is discussed. To enable low-latency coupling, the proposed hybrid architecture connects quantum computations to hardware implementations of timing critical classical computations and utilizes established hardware/software co-design patterns to interface higher-level classical computations. Experimental evidence of noise effects on state-of-the-art quantum hardware is presented for the case of solving partial differential equations. This supports the conclusion that frequent interaction between short and shallow quantum and classical computations is necessary even for loosely-coupled hybrid applications under these circumstances, strengthening the case for a low-latency, high-bandwidth quantum-classical interface as proposed in this thesis.
This paper proposes a descriptive language called QHDL, akin to VHDL, to program gate-based quantum computing systems. Unlike other popular quantum programming languages, QHDL targets low-level quantum computing programming and aims to provide a common framework for programming FPGAs and gate-based quantum computing systems. The paper presents an initial implementation and design principles of the QHDL framework, including a compiler and quantum computer simulator. We discuss the challenges of low-level integration of streaming models and quantum computing for programming FPGAs and gate-based quantum computing systems.
The quantum algorithms could efficiently solve problems having exponential classical solutions [8]. The circuit model is considered as the most feasible implementation of the quantum algorithms [17]. This paper tries to find common ground between classical circuit design techniques and quantum computation, by identifying quantum circuit specification and simulation tools under the form of Hardware Description Languages (HDLs). The HDL-based simulation approach could reduce the complexity of quantum circuit simulation, by considering entanglement as the main source of gate-level simulation complexity, and isolating it in an automated manner. This is possible by taking advantage of the HDL feature of describing a circuit with both structural and functional architectures. We also performed an analysis of our methodology effectiveness, for the arithmetic circuits involved in Shor's algorithm and the circuits implementing Grover's algorithm. Our method is further improved by an entangled representation avoidance technique called 'bubble logic insertion'.
Work is in progress throughout the globe to efficiently use the potential of the quantum theory of computation over their classical counterpart and hence there is a need of building quantum computing hardware. The target of building quantum computers can be achieved if we have better tools for the design of quantum hardware. Quantum circuit simulators are tools for the logic verification of quantum circuits and they can be an essential component of quantum CAD tools in the future. This work is the extension of the previous work by the authors, in order to increase the efficiency of the simulator and to incorporate more components in the gate library. In this paper we have proposed an efficient simulator which can simulate a quantum circuit specified using the proposed quantum hardware descriptive language (QHDL).
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Quantum computing is often treated as an experimental add-on: it is often loosely coupled to classical infrastructure through high-level interpreted languages, cloud-based orchestration and physical measurement hardware. However, future deployments in both high-performance computing (HPC) and embedded environments will demand tighter integration for lower latencies, stronger determinism, and architectural consistency. We propose a vertically integrated quantum systems architecture that treats quantum accelerators as peripheral system components. A central element is the Quantum Abstraction Layer (QAL), introduced at the kernel level of the operating system. This design enables real-time, low-latency, and high-throughput interaction between quantum and classical resources and opens the door for robust scheduling, resource management, and cross-stack optimisation. Kernel-space integration is not merely a technical curiosity—it is a necessity. For HPC, it enables scalable, heterogeneous workloads; for embedded systems, it provides a foundation for future quantum deployments far beyond scripting-based control interfaces. We present early-stage results including a virtual QPU model integrated into a QEMU-based prototype system. The architecture is validated through functional emulation and time-accurate FPGA simulations, enabling realistic evaluation of hybrid system performance and quantum advantage scenarios. Our work lays the groundwork for a system-level co-design methodology tailored for the next generation of quantum-classical computing.