arXiv:2503.18868 · International Conference in Electronic Engineering & Information Technology (EEITE)
Hardware-level Interfaces for Hybrid Quantum-Classical Computing Systems
Konstantinos Rallis, Ioannis Liliopoulos, Evangelos Tsipas, Georgios D. Varsamis, Nikolaos Melissourgos, Ioannis G. Karafyllidis, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis
The technology of Quantum Computing (QC) is continuously evolving, as researchers explore new technologies and the public gains access to quantum computers with an increasing number of qubits. In addition, the research community and industry are increasingly interested in the potential use, application, and contribution of QCs to large-scale problems in the real world as a result of this technological enhancement. QCs operations are based on quantum mechanics, and their special properties are mainly exploited to solve computationally intensive problems in polynomial time, problems that are commonly unsolvable, even by High-Performance Computing systems (HPCs) in a feasible time. However, since QCs cannot perform as general-purpose computing machines, alternative computational approaches aiming to boost further their enormous computing abilities are requested, and their combination as an additional computing resource to HPC systems is considered as one of the most promising ones. In the proposed hybrid HPCs, the Quantum Processing Units (QPUs), similar to GPUs and CPUs, target specific problems that, through Quantum Algorithms, can exploit quantum properties like quantum entanglement and superposition to achieve substantial performance gains from the HPC point of view. This interconnection between classical HPC systems and QCs towards the creation of Hybrid Quantum-Classical computing systems is neither straightforward nor standardized while crucial for unlocking the real potential of QCs and achieving real performance improvements. The interconnection between the classical and quantum systems can be performed in the hardware, software (system), or application layer. In this study, a concise overview of the existing architectures for the interconnection interface between HPCs and QCs is provided, focusing mainly on hardware approaches that enable effective hybrid quantum-classical operation.
The technology of Quantum Computing (QC) is continuously evolving, as researchers explore new technologies and the public gains access to quantum computers with an increasing number of qubits. In addition, the research community and industry are increasingly interested in the potential use, application, and contribution of QCs to large-scale problems in the real world as a result of this technological enhancement. QCs operations are based on quantum mechanics, and their special properties are mainly exploited to solve computationally intensive problems in polynomial time, problems that are commonly unsolvable, even by High-Performance Computing systems (HPCs) in a feasible time. However, since QCs cannot perform as general-purpose computing machines, alternative computational approaches aiming to boost further their enormous computing abilities are requested, and their combination as an additional computing resource to HPC systems is considered as one of the most promising ones. In the proposed hybrid HPCs, the Quantum Processing Units (QPUs), similar to GPUs and CPUs, target specific problems that, through Quantum Algorithms, can exploit quantum properties like quantum entanglement and superposition to achieve substantial performance gains from the HPC point of view. This interconnection between classical HPC systems and QCs towards the creation of Hybrid Quantum-Classical computing systems is neither straightforward nor standardized while crucial for unlocking the real potential of QCs and achieving real performance improvements. The interconnection between the classical and quantum systems can be performed in the hardware, software (system), or application layer. In this study, a concise overview of the existing architectures for the interconnection interface between HPCs and QCs is provided, focusing mainly on hardware approaches that enable effective hybrid quantum-classical operation.
High-performance computing (HPC) has evolved over decades through multiple architectural transitions, from vector supercomputers to massively parallel CPU clusters and GPU-accelerated systems, continuously expanding the frontier of scientific discovery. With the emergence of quantum processing units (QPUs) as practical computational accelerators, a new opportunity arises to further extend this trajectory by integrating quantum and classical computing paradigms. Building on the emerging vision of Quantum Integrated High-Performance Computing (QHPC), this paper contributes a full-stack layered architecture that integrates QPUs as first-class accelerators within, not merely alongside, the classical HPC software and hardware stack, with tight, on-premise quantum-classical coupling as its defining characteristic. The architecture comprises of unified resource management, quantum-aware scheduling, hybrid workflow orchestration, middleware and programming abstraction, interconnect technologies, and a tiered execution model enabling seamless workload partitioning across classical and quantum backends. A central aspect of this architecture is a strong user requests abstraction layer that exposes heterogeneous resources through a unified job submission interface, similar in spirit to existing schedulers such as Slurm, allowing users to describe workloads in a consistent template independent of underlying compute type or location. Drawing insights from prior accelerator integration eras, we outline how QHPC can support emerging workloads in quantum chemistry, materials discovery, combinatorial optimization, and climate modeling. We conclude by highlighting open challenges in building scalable, reliable, and programmable quantum-classical infrastructures that seamlessly connect global users to heterogeneous compute resources for future quantum-classical HPC ecosystems.
The connection and eventual integration of High-Performance Computing (HPC) with Quantum Computing (QC) represents a transformative advancement in computational technology, promising significant enhancements in solving complex, previously intractable problems. This manuscript provides a comprehensive overview of the current state of HPC-QC interfacing, detailing architectural methodologies, software stack developments, middleware functionalities, and hardware integration strategies. It critically assesses existing hardware-level integration models, ranging from standalone and loosely-coupled architectures to tightly-integrated and on-node systems. The software ecosystem is analyzed, highlighting prominent frameworks such as Qiskit, PennyLane, CUDA-Q, and middleware solutions like Pilot-Quantum, essential for seamless hybrid computing environments. Furthermore, the manuscript discusses practical applications in optimization, machine learning, and many-body dynamics, where hybrid HPC-QC systems can offer substantial advantages. It also describes existing challenges, including hardware limitations (coherence, scalability, connectivity), software maturity, communication overhead, resource management complexities, and cost factors. Finally, future directions towards tighter hardware and software integration are discussed, emphasizing ongoing research developments and emerging trends that promise to expand the capabilities and accessibility of hybrid HPC-QC systems.
High-performance computing (HPC) has evolved over decades through multiple architectural transitions, from vector supercomputers to massively parallel CPU clusters and GPU-accelerated systems, continuously expanding the frontier of scientific discovery. With the emergence of quantum processing units (QPUs) as practical computational accelerators, a new opportunity arises to further extend this trajectory by integrating quantum and classical computing paradigms. Building on the emerging vision of Quantum Integrated High-Performance Computing (QHPC), this paper contributes a full-stack layered architecture that integrates QPUs as first-class accelerators within, not merely alongside, the classical HPC software and hardware stack, with tight, on-premise quantum–classical coupling as its defining characteristic. The architecture comprises of unified resource management, quantum-aware scheduling, hybrid workflow orchestration, middleware and programming abstraction, interconnect technologies, and a tiered execution model enabling seamless workload partitioning across classical and quantum backends. A central aspect of this architecture is a strong user requests abstraction layer that exposes heterogeneous resources through a unified job submission interface, similar in spirit to existing schedulers such as Slurm, allowing users to describe workloads in a consistent template independent of underlying compute type or location. Drawing insights from prior accelerator integration eras, we outline how QHPC can support emerging workloads in quantum chemistry, materials discovery, combinatorial optimization, and climate modeling. We conclude by highlighting open challenges in building scalable, reliable, and programmable quantum–classical infrastructures that seamlessly connect global users to heterogeneous compute resources for future quantum–classical HPC ecosystems.
Quantum computers have demonstrated utility in simulating quantum systems beyond brute-force classical approaches. As the community builds on these demonstrations to explore using quantum computing for applied research, algorithms and workflows have emerged that require leveraging both quantum computers and classical high-performance computing (HPC) systems to scale applications, especially in chemistry and materials, beyond what either system can simulate alone. Today, these disparate systems operate in isolation, forcing users to manually orchestrate workloads, coordinate job scheduling, and transfer data between systems -- a cumbersome process that hinders productivity and severely limits rapid algorithmic exploration. These challenges motivate the need for flexible and high-performance Quantum-Centric Supercomputing (QCSC) systems that integrate Quantum Processing Units (QPUs), Graphics Processing Units (GPUs), and Central Processing Units (CPUs) to accelerate discovery of such algorithms across applications. These systems will be co-designed across quantum and classical HPC infrastructure, middleware, and application layers to accelerate the adoption of quantum computing for solving critical computational problems. We envision QCSC evolution through three distinct phases: (1) quantum systems as specialized compute offload engines within existing HPC complexes; (2) heterogeneous quantum and classical HPC systems coupled through advanced middleware, enabling seamless execution of hybrid quantum-classical algorithms; and (3) fully co-designed heterogeneous quantum-HPC systems for hybrid computational workflows. This article presents a reference architecture and roadmap for these QCSC systems.
The use of quantum processing units (QPUs) promises speed-ups for solving computational problems, but the quantum devices currently available possess only a very limited number of qubits and suffer from considerable imperfections. One possibility to progress towards practical utility is to use a co-design approach: Problem formulation and algorithm, but also the physical QPU properties are tailored to the specific application. Since QPUs will likely be used as accelerators for classical computers, details of systemic integration into existing architectures are another lever to influence and improve the practical utility of QPUs. In this work, we investigate the influence of different parameters on the runtime of quantum programs on tailored hybrid CPU-QPU-systems. We study the influence of communication times between CPU and QPU, how adapting QPU designs influences quantum and overall execution performance, and how these factors interact. Using a simple model that allows for estimating which design choices should be subjected to optimisation for a given task, we provide an intuition to the HPC community on potentials and limitations of co-design approaches. We also discuss physical limitations for implementing the proposed changes on real quantum hardware devices.
There is a great deal of focus on how quantum computing as an accelerator differs from other traditional high-performance computing (HPC) resources, including accelerators like GPUs and field-programmable gate arrays. In classical computing, how to design the interfaces that connect the different layers of the software stack, from the applications and high-level programming language description, through compilers and schedulers, and down to the hardware and gate level, has been critical. Likewise, quantum computing’s interfaces enable access to quantum technology as a viable accelerator. From the ideation of the quantum application to the manipulation of the quantum chip, each interface has its challenges. In this article, we discuss the structure of this set of quantum interfaces, their many similarities to the traditional HPC compilation stack, and how these interfaces impact the potential of quantum computers as HPC accelerators.