Hybrid quantum-classical algorithms have shown great promise in leveraging the computational potential of quantum systems.However, the efficiency of these algorithms is severely constrained by the limitations of current quantum hardware architectures.These architectures, which typically feature a decoupled design, lack both hardware support for low-latency communication and software support for fine-grained optimization.In this paper, we propose Qtenon, a tightly coupled system for efficient hybrid quantum-classical algorithm acceleration.Qtenon is composed of both hardware part and software part.To enable efficient communication and computation, the hardware part provides a unified memory hierarchy, an efficient quantum controller, as well as a multi-stage processing pipeline.The unified memory hierarchy functions as a communication buffer between host and quantum accelerators, with dedicated data paths and interfaces provided by the quantum controller.The multi-stage pipeline leverages hardware pipelines to fully exploit parallelism.To program hybrid quantum-classical algorithms on the hardware, our software part provides a set of instructions for data communication and computation.The instructions also enable fine-grained synchronization and efficient scheduling for quantum-host interaction.We design Qtenon as a RISC-V extended chip and implement it using Chisel.In evaluation, we achieve up to 14.9× end-to-end speedup compared to state-of-the-art work for hybrid quantum-classical algorithms.
Hybrid quantum-classical algorithms have shown great promise in leveraging the computational potential of quantum systems.However, the efficiency of these algorithms is severely constrained by the limitations of current quantum hardware architectures.These architectures, which typically feature a decoupled design, lack both hardware support for low-latency communication and software support for fine-grained optimization.In this paper, we propose Qtenon, a tightly coupled system for efficient hybrid quantum-classical algorithm acceleration.Qtenon is composed of both hardware part and software part.To enable efficient communication and computation, the hardware part provides a unified memory hierarchy, an efficient quantum controller, as well as a multi-stage processing pipeline.The unified memory hierarchy functions as a communication buffer between host and quantum accelerators, with dedicated data paths and interfaces provided by the quantum controller.The multi-stage pipeline leverages hardware pipelines to fully exploit parallelism.To program hybrid quantum-classical algorithms on the hardware, our software part provides a set of instructions for data communication and computation.The instructions also enable fine-grained synchronization and efficient scheduling for quantum-host interaction.We design Qtenon as a RISC-V extended chip and implement it using Chisel.In evaluation, we achieve up to 14.9× end-to-end speedup compared to state-of-the-art work for hybrid quantum-classical algorithms.
By exploiting quantum mechanical behavior, quantum computers have the potential to carry out classically hard computations, such as the prime factorization of integers, with disruptive, exponentially better efficiency, yet they struggle with classically simple task like integer addition. Hybrid applications, combining both quantum and classical computations, attempt to take advantage of the strength of both approaches while avoiding their weaknesses. In such applications, the design of the interface between quantum and classical computers deserves attention as a potential performance bottleneck. In this thesis, the design of a modular software stack for hybrid quantum/classical applications that is agnostic to the used quantum technology platform is developed both for high-level application-oriented as well as high-performance low-level use-cases. A hardware description language for quantum circuits derived from the industry standard VHDL language is proposed, and its usage in tightly-coupled hybrid applications, where quantum and classical computations overlap in time, is discussed. To enable low-latency coupling, the proposed hybrid architecture connects quantum computations to hardware implementations of timing critical classical computations and utilizes established hardware/software co-design patterns to interface higher-level classical computations. Experimental evidence of noise effects on state-of-the-art quantum hardware is presented for the case of solving partial differential equations. This supports the conclusion that frequent interaction between short and shallow quantum and classical computations is necessary even for loosely-coupled hybrid applications under these circumstances, strengthening the case for a low-latency, high-bandwidth quantum-classical interface as proposed in this thesis.
To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale super-linearly with number of qubits, which is critical to support scalability efforts in OC hardware.
One of the primary focuses in the rapidly changing scenery of quantum computing is one of the most promising methodologies for transgressing the current feat of quantum technologies: a better mix of quantum and classical paradigms of computations.This paper suggests a new hybrid quantum-classical processor architecture that augments the computational speed and enhances efficiency by utilizing powers emanating from the quantum and classical processing units.The architecture proposed in the study incorporates quantum processing units with classical processing units, with CPUs interfaced tightly to support dynamic task allocation with a view toward computational requirements.Hybrid processor design caters to the performance of quantum algorithms that usually involve classical preprocessing and postprocessing, such as the Variational Quantum Eigensolver and Quantum Approximate Optimization Algorithm.These algorithms are essential for any complicated optimization, the simulation of quantum systems, and applications in machine learning.We provide an insightful processor architecture design, understanding the communication protocol details between QPU and CPU, the scheduling mechanism for hybrid tasks, and the optimization techniques employed to minimize data transfer overhead while maximizing computational throughput.A lot of these implementation challenges, like quantum error correction, managing the coherence time, and classical-quantum data conversion, are something that innovations in hardware design and software algorithms can achieve.In this paper, the performance of the hybrid processor is, for the first time, fully benchmarked based on simulation and experimental setups.Resultsshow that this hybrid approach outperforms standalone quantum and classical processors on specific computational tasks by ten times in optimization problems and five times for machine learning.These include case studies showing that for some problems, the processor can solve real-world problems much more efficiently than any existing quantum or classical system.Such case studies include quantum chemistry simulations, cryptographic tasks, and training machine learning models.We turn to the scalability and flexibility of the hybrid processor to extend the horizon of these case studies and to bridge the gap between the current quantum computing capabilities and the race toward fully functional quantum computers.This new hybrid quantum-classical processor architecture makes significant progress in quantum computing by providing a pragmatic, workable solution for harnessing quantum mechanics but using the maturity of classical computing.The results show how to proceed with the research involving the hybrid system and the many potential applications of such systems across optimization, cryptography, and artificial intelligence.This study is significant as it offers a practical approach to overcoming the limitations of current quantum and classical processors, providing a pathway to more efficient and scalable computational solutions.
Scaling bottlenecks the making of digital quantum computers, posing challenges from both the quantum and the classical components. We present a classical architecture to cope with a comprehensive list of the latter challenges all at once , and implement it fully in an end-to-end system by integrating a multi-core RISC-V CPU with our in-house control electronics. Our architecture enables scalable, high-precision control of large quantum processors and accommodates evolving requirements of quantum hardware. A central feature is a microarchitecture executing quantum operations in parallel on arbitrary predefined qubit groups. Another key feature is a reconfigurable quantum instruction set that supports easy qubit re-grouping and instructions extensions. As a demonstration, we implement the widely-studied surface code quantum computing workflow, which is instructive for being demanding on both the controllers and the integrated classical computation. Our design, for the first time, reduces instruction issuing and transmission costs to constants, which do not scale with the number of qubits, without adding any overheads in decoding or dispatching. Our system uses a dedicated general-purpose CPU for both qubit control and classical computation, including syndrome decoding. Implementing recent theoretical proposals as decoding firmware that parallelizes general inner decoders, we can achieve unprecedented decoding capabilities of up to distances 47 and 67 with the currently available systems-on-chips for physical error rate p = 0.001 and p = 0.0001, respectively, all in just 1 μs.
High-performance computing (HPC) has evolved over decades through multiple architectural transitions, from vector supercomputers to massively parallel CPU clusters and GPU-accelerated systems, continuously expanding the frontier of scientific discovery. With the emergence of quantum processing units (QPUs) as practical computational accelerators, a new opportunity arises to further extend this trajectory by integrating quantum and classical computing paradigms. Building on the emerging vision of Quantum Integrated High-Performance Computing (QHPC), this paper contributes a full-stack layered architecture that integrates QPUs as first-class accelerators within, not merely alongside, the classical HPC software and hardware stack, with tight, on-premise quantum-classical coupling as its defining characteristic. The architecture comprises of unified resource management, quantum-aware scheduling, hybrid workflow orchestration, middleware and programming abstraction, interconnect technologies, and a tiered execution model enabling seamless workload partitioning across classical and quantum backends. A central aspect of this architecture is a strong user requests abstraction layer that exposes heterogeneous resources through a unified job submission interface, similar in spirit to existing schedulers such as Slurm, allowing users to describe workloads in a consistent template independent of underlying compute type or location. Drawing insights from prior accelerator integration eras, we outline how QHPC can support emerging workloads in quantum chemistry, materials discovery, combinatorial optimization, and climate modeling. We conclude by highlighting open challenges in building scalable, reliable, and programmable quantum-classical infrastructures that seamlessly connect global users to heterogeneous compute resources for future quantum-classical HPC ecosystems.
High-performance computing (HPC) has evolved over decades through multiple architectural transitions, from vector supercomputers to massively parallel CPU clusters and GPU-accelerated systems, continuously expanding the frontier of scientific discovery. With the emergence of quantum processing units (QPUs) as practical computational accelerators, a new opportunity arises to further extend this trajectory by integrating quantum and classical computing paradigms. Building on the emerging vision of Quantum Integrated High-Performance Computing (QHPC), this paper contributes a full-stack layered architecture that integrates QPUs as first-class accelerators within, not merely alongside, the classical HPC software and hardware stack, with tight, on-premise quantum–classical coupling as its defining characteristic. The architecture comprises of unified resource management, quantum-aware scheduling, hybrid workflow orchestration, middleware and programming abstraction, interconnect technologies, and a tiered execution model enabling seamless workload partitioning across classical and quantum backends. A central aspect of this architecture is a strong user requests abstraction layer that exposes heterogeneous resources through a unified job submission interface, similar in spirit to existing schedulers such as Slurm, allowing users to describe workloads in a consistent template independent of underlying compute type or location. Drawing insights from prior accelerator integration eras, we outline how QHPC can support emerging workloads in quantum chemistry, materials discovery, combinatorial optimization, and climate modeling. We conclude by highlighting open challenges in building scalable, reliable, and programmable quantum–classical infrastructures that seamlessly connect global users to heterogeneous compute resources for future quantum–classical HPC ecosystems.