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IEICE Transactions on Electronics

Evaluation of Low-Power Single-Flux-Quantum Circuits Fabricated with a 250 A/cm2 Nb/AlOx/Nb Josephson Junction Process Using a Dilution Refrigerator

Masamitsu Tanaka, Tomoki UEDA, Yoshihiro KITAGAWA, T. Satoh, Tsuyoshi YAMAMOTO

Published Apr 22, 2026• 0 citations
Publisher

Abstract

We report the measurement results of the low-power single-flux-quantum (SFQ) circuits below 20 mK using a dilution refrigerator. We have been developing the SFQ circuits using a lowered critical current density process (250 A/cm2) and low-voltage design (0.1–0.5 mV) toward digital signal processing near superconductor quantum bits. So far, we have designed several basic SFQ cells, including wiring elements, flip-flops, and logic gates, using the four Nb planarized layer process and obtained the correct operation at 300 mK. In this study, we tested several SFQ circuits aiming to evaluate the operation at the mixing chamber stage of a dilution refrigerator. Our experimental results show that there was almost no change of device parameters, such as critical current values of Josephson junctions, or operating margins of the basic cells between 300 mK and 16 mK.

DOI
10.1587/transele.2025sep0002

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We report the measurement results of the low-power single-flux-quantum (SFQ) circuits below 20 mK using a dilution refrigerator. We have been developing the SFQ circuits using a lowered critical current density process (250 A/cm2) and low-voltage design (0.1–0.5 mV) toward digital signal processing near superconductor quantum bits. So far, we have designed several basic SFQ cells, including wiring elements, flip-flops, and logic gates, using the four Nb planarized layer process and obtained the correct operation at 300 mK. In this study, we tested several SFQ circuits aiming to evaluate the operation at the mixing chamber stage of a dilution refrigerator. Our experimental results show that there was almost no change of device parameters, such as critical current values of Josephson junctions, or operating margins of the basic cells between 300 mK and 16 mK.
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Superconductor single-flux-quantum (SFQ) integrated circuits can provide classical, general-purpose digital processing at cryogenic temperature near quantum bits. We report high-frequency operation of low-power SFQ circuits using a lowered critical current density fabrication process and low-voltage design. We are developing a standard-cell library with integrated devices featuring four planarized Nb layers and a Pd resistor layer. SFQ shift registers successfully operated at up to 11 GHz at 0.3 K. The measured operating frequency is sufficient for SFQ-based digital controlling of quantum bits using impulse-shaped voltage pulses.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.
As quantum computing processors increase in size, there is growing interest in developing cryogenic electronics to overcome significant challenges to system scaling. Single flux-quantum (SFQ) circuits offer a promising alternative to remote, bulky, and power-hungry room temperature electronics. To meet the need for digital qubit control, readout, and co-processing, SFQ circuits must be adapted to operate at millikelvin temperatures near quantum processors. SEEQC's SFQuClass digital quantum management approach proximally places energy-efficient SFQ (ERSFQ) circuits and qubits in a multi-chip module. This enables extremely low power dissipation, compatible with a typical dilution cryostat's limited cooling power, while maintaining high processing speed and low error rates. We report on systematic testing from 4 K to 10 mK of a comprehensive set of ERSFQ cells, as well as more complex circuits such as programmable counters and demultiplexers used in digital qubit control. We compare the operating margins and error rates of these circuits and find that, at millikelvin, bias margins decrease and the center of the margins (i.e., the optimal bias current value) increases by ~15%, compared to 4.2 K. The margins can be restored by thermal annealing by reducing Josephson junction (JJ) critical current Ic. To provide guidance for how circuit parameters vary from 4.2 K to millikelvin, relevant analog process control monitors (PCMs) were tested in the temperature range of interest. The measured JJ critical current (of the PCM JJ arrays) increases by ~15% when decreasing temperature from 4.2 K to millikelvin, in good agreement with both theory and the empirically measured change in the center of bias margins for the tested digital circuits.