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HEXA-SUPER: Superconducting Logic Processor at $\sigma^2 = 144$ GHz with n=6 Cryogenic Architecture

TECS-L Project

Published Apr 4, 2026• 0 citations
Publisher

Abstract

N=6 architecture paper: HEXA-SUPER: Superconducting Logic Processor at $\sigma^2 = 144$ GHz with n=6 Cryogenic Architecture

DOI
10.5281/zenodo.19422083

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HEXA-SUPER: Superconducting Logic Processor at σ2=144\sigma^2 = 144σ2=144 GHz with n=6 Cryogenic Architecture
N=6 architecture paper: HEXA-SUPER: Superconducting Logic Processor at σ2=144\sigma^2 = 144σ2=144 GHz with n=6 Cryogenic Architecture
We present HEXA-SUPER, a superconducting logic processor operating at \sigma^2 = 144 GHz clock frequency---28.8\times beyond the CMOS frequency wall of \sim5 GHz---with every design parameter derived from the arithmetic functions of the perfect number n = 6. The processor employs Rapid Single Flux Quantum (RSFQ) logic at 144 GHz for peak throughput and Adiabatic Quantum Flux Parametron (AQFP) logic at \sigma \cdot \tau = 48 GHz for energy-efficient bulk computation. The architecture comprises \sigma = 12 superconducting cores, each with \sigma - \tau = 8 ALUs and a \sigma = 12-stage pipeline, yielding 96 total ALUs clocked at 144 GHz. A \tau = 4-level cryogenic memory hierarchy spans RSFQ SRAM (2^{\sigma} = 4 KB L1), cryo-DRAM (\sigma \cdot J_2 = 288 KB L2), Josephson junction RAM (\sigma^
Superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising technology for cryogenic applications (e.g., quantum computing, astronomy, metrology) thanks to its ultra-fast and low-energy characteristics. Therefore, recent efforts in SFQ-based computing have focused on developing fast and low-power SFQ processors for cryogenic applications. However, there still has been little progress toward a convincing SFQ processor design due to the critical performance challenges originating from its extremely deep pipeline. In this paper, we propose a super-fast and low-power in-order SFQ processor by tackling the challenges from the deep pipeline. First, we develop a minimal-depth SFQ processor pipeline with novel architecture-level ideas. Next, we conduct in-depth performance analyses and identify three real performance bottlenecks in the deeply pipelined SFQ processors (i.e., stall/flush logic, RAW stall, fetch unit). Finally, we propose SuperCore, our super-fast SFQ-based processor architecture, with three SFQ-friendly solutions that effectively resolve the identified bottlenecks. With our solutions applied, SuperCore achieves 11 times speed-up over the SFQ processor baseline. In addition, SuperCore achieves six times speed-up and consumes up to 193 times less power compared to in-order CMOS processors running at 4K.
The gap between logic speed and memory access is a growing problem in all computing systems and it is exacerbated for ultra-high speed processors such as the proposed cryogenic Rapid Single Flux Quantum (RSFQ) logic working at 50 .100 GHz. The Superconducting Technology Assessment (STA) Panel considered two levels in a hierarchy of cryogenic memory located off of the processor chip. The first level of off-chip memory would be located on the MCM at 4 Kelvin (4 K) with the processor chip in order to minimize propagation-time delays. We are planning for a 1 Mb memory for this stage. The second-level memory would be much larger and could be located on a more efficient refrigerator stage at 40-77 K.