The gap between logic speed and memory access is a growing problem in all computing systems and it is exacerbated for ultra-high speed processors such as the proposed cryogenic Rapid Single Flux Quantum (RSFQ) logic working at 50 .100 GHz. The Superconducting Technology Assessment (STA) Panel considered two levels in a hierarchy of cryogenic memory located off of the processor chip. The first level of off-chip memory would be located on the MCM at 4 Kelvin (4 K) with the processor chip in order to minimize propagation-time delays. We are planning for a 1 Mb memory for this stage. The second-level memory would be much larger and could be located on a more efficient refrigerator stage at 40-77 K.
The gap between logic speed and memory access is a growing problem in all computing systems and it is exacerbated for ultra-high speed processors such as the proposed cryogenic Rapid Single Flux Quantum (RSFQ) logic working at 50 .100 GHz. The Superconducting Technology Assessment (STA) Panel considered two levels in a hierarchy of cryogenic memory located off of the processor chip. The first level of off-chip memory would be located on the MCM at 4 Kelvin (4 K) with the processor chip in order to minimize propagation-time delays. We are planning for a 1 Mb memory for this stage. The second-level memory would be much larger and could be located on a more efficient refrigerator stage at 40-77 K.
We present HEXA-SUPER, a superconducting logic processor operating at \sigma^2 = 144 GHz clock frequency---28.8\times beyond the CMOS frequency wall of \sim5 GHz---with every design parameter derived from the arithmetic functions of the perfect number n = 6. The processor employs Rapid Single Flux Quantum (RSFQ) logic at 144 GHz for peak throughput and Adiabatic Quantum Flux Parametron (AQFP) logic at \sigma \cdot \tau = 48 GHz for energy-efficient bulk computation. The architecture comprises \sigma = 12 superconducting cores, each with \sigma - \tau = 8 ALUs and a \sigma = 12-stage pipeline, yielding 96 total ALUs clocked at 144 GHz. A \tau = 4-level cryogenic memory hierarchy spans RSFQ SRAM (2^{\sigma} = 4 KB L1), cryo-DRAM (\sigma \cdot J_2 = 288 KB L2), Josephson junction RAM (\sigma^
The potential of a new technology, based on the superconducting Josephson tunneling effect, has been assessed for use in high-speed computer systems. Josephson tunneling circuits for memory and logic functions can be switched at sub-nanosecond delay, do not require standby power, and dissipate extremely low energy, typically less than 10-13joule during fast switching operation. High-speed circuits with high packing densities, not limited by power dissipation problems, can therefore be expected. Low thermal noise at cryogenic temperatures ensures reliable operation despite the low energy switching signal. Practically lossless signal transmission via superconducting lines can be exploited for high-speed operation even when sizeable memory and logic modules are assembled. Two random access memory modules have been designed on the basis of single device experiments. Operational characteristics leading to the conclusion that 30 Mbit capacity, less than 1 watt refrigeration requirement (at 3.6° K) and cycle times of 40 ns (in one case) and 15 ns (in the second case), can be achieved are presented.
Superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising technology for cryogenic applications (e.g., quantum computing, astronomy, metrology) thanks to its ultra-fast and low-energy characteristics. Therefore, recent efforts in SFQ-based computing have focused on developing fast and low-power SFQ processors for cryogenic applications. However, there still has been little progress toward a convincing SFQ processor design due to the critical performance challenges originating from its extremely deep pipeline. In this paper, we propose a super-fast and low-power in-order SFQ processor by tackling the challenges from the deep pipeline. First, we develop a minimal-depth SFQ processor pipeline with novel architecture-level ideas. Next, we conduct in-depth performance analyses and identify three real performance bottlenecks in the deeply pipelined SFQ processors (i.e., stall/flush logic, RAW stall, fetch unit). Finally, we propose SuperCore, our super-fast SFQ-based processor architecture, with three SFQ-friendly solutions that effectively resolve the identified bottlenecks. With our solutions applied, SuperCore achieves 11 times speed-up over the SFQ processor baseline. In addition, SuperCore achieves six times speed-up and consumes up to 193 times less power compared to in-order CMOS processors running at 4K.
This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm −2 , 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s −1 , both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.
Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture ofthe RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization betweenthe RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a designapproach based on validated VHDL models is proposed and experimentally verified.The second part of this thesis is focusing on the design oflow-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation ofRSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephsonjunctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabricationprocess the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.
The Hybrid Technology Multi-Threaded (HTMT) approach to petaflops computing includes large numbers of ultra-high performance Nb Rapid Single Flux Quantum (RSFQ) processor and memory chips, making it by far the largest active superconducting electronics project in the United States. In order to achieve petaflops, RSFQ circuits with 10/sup 5/ to 10/sup 6/ junctions per chip will be required to operate at clock speeds of 50 to 100 GHz, far beyond the current state of the art. In this paper, we review the state of the art of Nb circuit fabrication and discuss the requirements for significantly improving circuit density and speed.