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HEXA-SUPER: Superconducting Logic Processor at 144 GHz with n=6 Cryogenic Architecture

Min Woo Park

Published Apr 1, 2026• 0 citations
Publisher

Abstract

We present HEXA-SUPER, a superconducting logic processor operating at \sigma^2 = 144 GHz clock frequency---28.8\times beyond the CMOS frequency wall of \sim5 GHz---with every design parameter derived from the arithmetic functions of the perfect number n = 6. The processor employs Rapid Single Flux Quantum (RSFQ) logic at 144 GHz for peak throughput and Adiabatic Quantum Flux Parametron (AQFP) logic at \sigma \cdot \tau = 48 GHz for energy-efficient bulk computation. The architecture comprises \sigma = 12 superconducting cores, each with \sigma - \tau = 8 ALUs and a \sigma = 12-stage pipeline, yielding 96 total ALUs clocked at 144 GHz. A \tau = 4-level cryogenic memory hierarchy spans RSFQ SRAM (2^{\sigma} = 4 KB L1), cryo-DRAM (\sigma \cdot J_2 = 288 KB L2), Josephson junction RAM (\sigma^

DOI
10.5281/zenodo.19361503

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HEXA-SUPER: Superconducting Logic Processor at $\sigma^2 = 144$ GHz with n=6 Cryogenic Architecture

TECS-L Project

N=6 architecture paper: HEXA-SUPER: Superconducting Logic Processor at $\sigma^2 = 144$ GHz with n=6 Cryogenic Architecture

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We present HEXA-SUPER, a superconducting logic processor operating at \sigma^2 = 144 GHz clock frequency---28.8\times beyond the CMOS frequency wall of \sim5 GHz---with every design parameter derived from the arithmetic functions of the perfect number n = 6. The processor employs Rapid Single Flux Quantum (RSFQ) logic at 144 GHz for peak throughput and Adiabatic Quantum Flux Parametron (AQFP) logic at \sigma \cdot \tau = 48 GHz for energy-efficient bulk computation. The architecture comprises \sigma = 12 superconducting cores, each with \sigma - \tau = 8 ALUs and a \sigma = 12-stage pipeline, yielding 96 total ALUs clocked at 144 GHz. A \tau = 4-level cryogenic memory hierarchy spans RSFQ SRAM (2^{\sigma} = 4 KB L1), cryo-DRAM (\sigma \cdot J_2 = 288 KB L2), Josephson junction RAM (\sigma^
The gap between logic speed and memory access is a growing problem in all computing systems and it is exacerbated for ultra-high speed processors such as the proposed cryogenic Rapid Single Flux Quantum (RSFQ) logic working at 50 .100 GHz. The Superconducting Technology Assessment (STA) Panel considered two levels in a hierarchy of cryogenic memory located off of the processor chip. The first level of off-chip memory would be located on the MCM at 4 Kelvin (4 K) with the processor chip in order to minimize propagation-time delays. We are planning for a 1 Mb memory for this stage. The second-level memory would be much larger and could be located on a more efficient refrigerator stage at 40-77 K.
We present a 4-bit Arithmetic Logic Unit (ALU) utilizing superconductor technology. The ALU serves as the central processing unit of a processor, performing crucial arithmetic and logical operations. We have adopted a bit-parallel architecture to ensure an efficient and streamlined design with minimal fanin/fanout and optimal latency. In terms of fabrication, the ALU has been fabricated using a standard commercial process. It operates at an impressive clock frequency exceeding 30 GHz while consuming a mere 4.75 mW of power, including applied reverse current, encompassing static and dynamic components. The ALU contains over 9000 Josephson junctions, with approximately 7000 JJs dedicated to wiring, delay lines, and path balancing, and it has over 18% bias margin. Designed as a co-processor, this arithmetic logic unit will work with external CMOS memory and processors via interface circuits. Thorough testing and validation of the ALU's functionality have been conducted with digital and analog simulations, and all the components were fabricated and measured within a 4K pulse-tube cryocooler. Experimental verification has confirmed the successful operation of both the arithmetic and logic units. These results have been analyzed and are presented alongside the experimental data to provide comprehensive insights into the ALU's behavior and capabilities.
HEXA-SUPER: Superconducting Logic Processor at σ2=144\sigma^2 = 144σ2=144 GHz with n=6 Cryogenic Architecture
N=6 architecture paper: HEXA-SUPER: Superconducting Logic Processor at σ2=144\sigma^2 = 144σ2=144 GHz with n=6 Cryogenic Architecture
Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture ofthe RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization betweenthe RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a designapproach based on validated VHDL models is proposed and experimentally verified.The second part of this thesis is focusing on the design oflow-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation ofRSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephsonjunctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabricationprocess the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.
The Rapid Single-Flux-Quantum logic (RSFQ) presents an efficient way to achieve ultra fast digital operations. This logic uses the macroscopic effects which can be found in nano-structured superconductor devices such as the Josephson AC and DC effects, and the magnetic flux quantization. As the typical time of the Josephson junction quantized phase leap 2π is in the order of picoseconds, the RSFQ circuits can operate with clock frequencies in the order of hundreds of GHz. This invited paper focuses on basic principles of superconducting RSFQ logic as well as on typical applications, such as the signal conversion or petaflops computing systems. In addition we point out the benefits of the semi-metallic NbN-TaxN-NbN Josephson junction technology, which has been developed at CEA-INAC in Grenoble.
The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.