As superconducting quantum processors scale beyond thousands of qubits, manual layout methods pose the primary bottleneck to industrial deployment. Traditional quantum electronic design automation (EDA) tools emphasize component-level modeling but lack full-chip integration for scalable systems. This work formulates scalable superconducting quantum chip design as a geometric constraint satisfaction problem (CSP) and introduces GeoSynth, a constraint-aware automation framework to accelerate scalable quantum chip design. By leveraging global symmetry and local similarity of quantum chip, GeoSynth enables hierarchical constraint decomposition through four novel algorithms: adaptive launch pad allocation (GeoSynth-ALA), systematic component correspondence (GeoSynth-SCC), scalable template-based routing synthesis (GeoSynth-TRS), and global constraint propagation (GeoSynth-GCP). Implemented in EDA-Q, GeoSynth delivers an end-to-end automation flow for a 156-qubit flip-chip processor in 2,882 seconds. This represents a 2× speedup over a prior method that addressed only the routing subproblem for 64 qubits, and is crowned by the first fabrication validation of an automatically generated large-scale layout, achieving a T1 coherence time of 69.24 μs. Beyond fabrication validation, GeoSynth demonstrates robust scalability by successfully generating layouts for diverse configurations spanning 64 to 620 qubits across multiple architectural variants, confirming its capability to handle industrially relevant scales. GeoSynth’s efficient, constraint-driven automation offers a scalable solution for quantum hardware industrialization.
As superconducting quantum processors scale beyond thousands of qubits, manual layout methods pose the primary bottleneck to industrial deployment. Traditional quantum electronic design automation (EDA) tools emphasize component-level modeling but lack full-chip integration for scalable systems. This work formulates scalable superconducting quantum chip design as a geometric constraint satisfaction problem (CSP) and introduces GeoSynth, a constraint-aware automation framework to accelerate scalable quantum chip design. By leveraging global symmetry and local similarity of quantum chip, GeoSynth enables hierarchical constraint decomposition through four novel algorithms: adaptive launch pad allocation (GeoSynth-ALA), systematic component correspondence (GeoSynth-SCC), scalable template-based routing synthesis (GeoSynth-TRS), and global constraint propagation (GeoSynth-GCP). Implemented in EDA-Q, GeoSynth delivers an end-to-end automation flow for a 156-qubit flip-chip processor in 2,882 seconds. This represents a 2× speedup over a prior method that addressed only the routing subproblem for 64 qubits, and is crowned by the first fabrication validation of an automatically generated large-scale layout, achieving a T1 coherence time of 69.24 μs. Beyond fabrication validation, GeoSynth demonstrates robust scalability by successfully generating layouts for diverse configurations spanning 64 to 620 qubits across multiple architectural variants, confirming its capability to handle industrially relevant scales. GeoSynth’s efficient, constraint-driven automation offers a scalable solution for quantum hardware industrialization.
Superconducting circuits have emerged as one of the most promising and scalable platforms for quantum com- puting, with substantial industrial adoption driving qubit counts steadily upward. Yet the layout of the corresponding chips is still primarily performed manually, consuming multiple days or weeks of expert effort, even for moderately sized designs. Existing automation approaches sidestep this bottleneck by simplifying the underlying problem and relaxing physical constraints. Therefore, they fall short of fabrication-ready results. To overcome this scalability wall without such compromises, we first introduce a formal abstraction that translates physical device characteristics into a rigorous geometric problem formulation. This abstraction bridges physical realization and design automation. Building upon this abstraction, we then propose a three-stage design automation flow comprising geometry-aware global partitioning, ILP-based port assignment, and a hierarchical routing pipeline. Evaluations conducted by our interdisciplinary team of design au- tomation researchers and superconducting hardware experts con- firm that the resulting flow produces complete, manufacturing- ready layouts that comply with the physical design rules at the push of a button. That is, it operates fully automatically within seconds to a few minutes, and solves complex instances up to 25x faster than the state of the art. All methods are released as the fully open-source tool mqt-scpd as part of the Munich Quantum Toolkit, providing the first readily usable, end- to-end design flow for planar superconducting quantum chips that explicitly addresses the underlying physical characteristics and requirements.
Superconducting quantum computing is advancing toward the thousand- and even million-qubit regime, making wafer-scale fabrication an essential pathway for achieving large-scale, cost-effective quantum processors. This manufacturing paradigm imposes new requirements on quantum-chip electronic design automation (Q-EDA): design tools must not only generate layouts (GDSII files) that satisfy quantum-circuit physical constraints but also ensure that the design data can be seamlessly converted into a complete set of manufacturing files executable by a wafer foundry, thereby enabling reliable translation from design intent to physical chip. This paper focuses on this critical data-conversion pipeline and presents a systematic treatment of the Q-EDA technology stack for wafer-scale fabrication. Starting from GDSII as the single authoritative data source, we analyze the key stages including process-design-kit (PDK)-based design rule checking (DRC), layout-versus-schematic (LVS) verification, design for manufacturability (DFM) optimization, wafer layout planning, and mask data preparation (MDP). We describe the concrete architecture of a Q-EDA system, present nine quantum-specific DRC rules together with their physical underpinnings and a multi-layer process stack model, and benchmark the manufacturing data-flow coverage of mainstream Q-EDA tools. Finally, we discuss the core challenges and future directions in this field.
Electronic Design Automation (EDA) plays a crucial role in classical chip design and significantly influences the development of quantum chip design. However, traditional EDA tools cannot be directly applied to quantum chip design due to vast differences compared to the classical realm. Several EDA products tailored for quantum chip design currently exist, yet they only cover partial stages of the quantum chip design process instead of offering a fully comprehensive solution. Additionally, they often encounter issues such as limited automation, steep learning curves, challenges in integrating with actual fabrication processes, and difficulties in expanding functionality. To address these issues, we developed a full-stack EDA tool specifically for quantum chip design, called EDA-Q. The design workflow incorporates functionalities present in existing quantum EDA tools while supplementing critical design stages such as device mapping and fabrication process mapping, which users expect. EDA-Q utilizes a unique architecture to achieve exceptional scalability and flexibility. The integrated design mode guarantees algorithm compatibility with different chip components, while employing a specialized interactive processing mode to offer users a straightforward and adaptable command interface. Application examples demonstrate that EDA-Q significantly reduces chip design cycles, enhances automation levels, and decreases the time required for manual intervention. Multiple rounds of testing on the designed chip have validated the effectiveness of EDA-Q in practical applications.
Quantum Electronic Design Automation (Q-EDA) is emerging as quantum chips move from laboratory prototypes to scalable engineering systems. This paper argues that superconducting quantum chip design is approaching a "SPICE moment" similar to early classical EDA, where growing qubit scale, control complexity, frequency planning, packaging, process variation, and cryogenic measurement feedback require a shift from experience-based design to model-driven engineering. We propose a Quantum Chip Paradigm Framework that treats Q-EDA not only as software, but as part of the quantum chip development paradigm. Unlike classical HDL-first design, quantum chip design must begin with physical structures such as Josephson junctions, resonators, couplers, readout elements, control lines, and packaging environments. The framework emphasizes PCell-based modeling, SPICE-Q simulation, Quantum PDKs, and design-technology-measurement co-optimization. We further outline a hierarchical Q-EDA system spanning physical structures, qubit PCells, logical qubits, quantum arithmetic, functional quantum IP, and Quantum SoC systems. The key goal is to turn physical models, layout rules, simulation results, fabrication data, and measurement feedback into reusable and auditable engineering objects for large-scale quantum processors and fault-tolerant quantum computing.
Routing design is an important aspect in aiding the completion of the Quantum Processing Unit (QPU) layout design for large-scale superconducting quantum processors. One of the research focuses is how to generate reliable routing schemes within a short time. In this study, we propose a superconducting quantum processor auto-routing method for supporting scalable architecture, which is mainly implemented through the bidirectional A star algorithm, the backtracking algorithm, and the greedy strategy. By using this method, the number of crossovers and corners can be reduced while efficiently completing the processor routing. To verify the effectiveness of our method, we selected 5 types of qubit numbers for processor routing experiments. The experimental results show that compared to the improved A star algorithm of Qiskit Metal, our method reduces the average execution time by at least 43.61% and 41.68% in serial and parallel, respectively. Compared with four other routing algorithms, our method has a minimum average reduction of 10.63% and 1.21% in the number of crossovers and corners, respectively. In addition, our method supports the processor routing design of planar and flip-chip architectures, and can automatically process both airbridge and insulation types of crossovers. Therefore, our method can provide efficient and reliable automated routing design to assist the development of large-scale superconducting quantum processors.
This paper proposes a fabless quantum-chip design and production architecture for superconducting quantum computing, centered on the SPICE-Q multiphysics simulation framework. The proposed ecosystem connects process-certified quantum PDKs, parameterized device cells, traceable model cards, SPICE-Q physical modeling languages, unified Q-EDA flows, foundry sign-off rules, cryogenic test feedback, and reusable quantum IP. In this model, design firms do not merely outsource fabrication; they prepare verified tape-outs under standardized process constraints and calibrated physical models. Its economic value lies in reducing repetitive device debugging, process exploration, and low-level layout effort, while its feasibility depends on PDK maturity, foundry yield, cryogenic test throughput, model-prediction accuracy, data-feedback mechanisms, and IP licensing boundaries. We argue that superconducting quantum chips can move from the current largely vertically integrated development model toward a fabless-foundry ecosystem only when hardware design is supported by standardized, verifiable, and reusable software and process interfaces. The required pillars are certified PDKs, PCell-based parameterized design, SPICE-Q cross-physics simulation, end-to-end Q-EDA automation, and a tradable quantum-IP market. By adapting lessons from the classical semiconductor industry to quantum hardware, this framework defines a path toward scalable, manufacturable, and commercially reusable superconducting quantum-chip design.