Description / Abstract Abstract Current Quantum Error Correction (QEC) protocols, such as the Surface Code, are typically optimized for Markovian noise models where errors are independent and identically distributed. We demonstrate that superconducting qubit architectures are susceptible to a specific class of non-Markovian correlated drift that remains undetectable by standard stabilizer measurements until it induces a catastrophic coherence collapse. We analytically derive this failure mode as a Fisher Information Horizon Limit, proving that an estimator optimizing solely for instantaneous gate fidelity experiences a divergence in variance regarding long-term structural drift. We model this "Hyper-Stable" regime as a system approaching an Exceptional Point (EP) in its effective non-Hermitian Hamiltonian. To mitigate this, we propose a control architecture utilizing a Systolic Drift Monitor (SDM) that integrates the geometric Berry phase of the noise history. By implementing a periodic Frame Update Unitary (conceptually isomorphic to basis rotation) on a dual-rail encoded subspace, we convert latent non-Markovian drift into observable execution variance, allowing for real-time suppression of the spectral singularity. Implementation Details The proposed architecture is designed for deployment on FPGA-based quantum control stacks (e.g., Xilinx RFSoC). Simulation results demonstrate a significant improvement in effective coherence times under 1/{f^alpha} noise conditions (alpha = 0.95) by preventing the system from entering the null space of the stabilizer code. The hardware logic is estimated to operate with a feedback latency of < 200 ns, well within the coherence time of standard transmon qubits. Keywords Quantum Error Correction, Superconducting Qubits, Non-Markovian Noise, Exceptional Points, Non-Hermitian Physics, FPGA Control, Dual-Rail Encoding, Fisher Information, Cramér-Rao Bound, Control Theory, Systolic Drift Monitor
Description / Abstract Abstract Current Quantum Error Correction (QEC) protocols, such as the Surface Code, are typically optimized for Markovian noise models where errors are independent and identically distributed. We demonstrate that superconducting qubit architectures are susceptible to a specific class of non-Markovian correlated drift that remains undetectable by standard stabilizer measurements until it induces a catastrophic coherence collapse. We analytically derive this failure mode as a Fisher Information Horizon Limit, proving that an estimator optimizing solely for instantaneous gate fidelity experiences a divergence in variance regarding long-term structural drift. We model this "Hyper-Stable" regime as a system approaching an Exceptional Point (EP) in its effective non-Hermitian Hamiltonian. To mitigate this, we propose a control architecture utilizing a Systolic Drift Monitor (SDM) that integrates the geometric Berry phase of the noise history. By implementing a periodic Frame Update Unitary (conceptually isomorphic to basis rotation) on a dual-rail encoded subspace, we convert latent non-Markovian drift into observable execution variance, allowing for real-time suppression of the spectral singularity. Implementation Details The proposed architecture is designed for deployment on FPGA-based quantum control stacks (e.g., Xilinx RFSoC). Simulation results demonstrate a significant improvement in effective coherence times under 1/{f^alpha} noise conditions (alpha = 0.95) by preventing the system from entering the null space of the stabilizer code. The hardware logic is estimated to operate with a feedback latency of < 200 ns, well within the coherence time of standard transmon qubits. Keywords Quantum Error Correction, Superconducting Qubits, Non-Markovian Noise, Exceptional Points, Non-Hermitian Physics, FPGA Control, Dual-Rail Encoding, Fisher Information, Cramér-Rao Bound, Control Theory, Systolic Drift Monitor
Description This work introduces the Systolic Drift Monitor (SDM), a universal hardware safety layer designed to address a fundamental limitation in real-time quantum error correction (QEC): the inability of finite-window decoders to detect slow, non-Markovian drift such as 1/f noise. We formalize this limitation as the Lag Horizon, an information-theoretic blind spot arising from finite memory and boundary-only observation. Using the Fisher-Blindness No-Go Theorem, we show that when error correlations extend beyond the decoder window, the Fisher information available to any windowed observer vanishes, rendering structural phase transitions statistically undetectable regardless of processing speed. To resolve this blindness, we propose the SDM as a minimal, architecture-independent hardware primitive that operates alongside—rather than within—the primary decoder. Implemented on 2025-era FPGA platforms (AMD Versal ACAP and Intel Agilex), the SDM performs deterministic, infinite-horizon integration of syndrome flux, restoring visibility to topological drift while maintaining constant latency. We analyze two experimentally relevant regimes: Superconducting dual-rail qubits, where the SDM functions as an asynchronous drift watchdog for long-timescale flux noise (>100 μs) despite sub-microsecond QEC cycles. Neutral atom processors, where large cycle times (>1 ms) allow the SDM to operate as a hard safety interlock, converting atom loss and leakage precursors into flagged erasures before logical failure. Simulation-based validation across surface codes and color codes demonstrates pre-symptomatic detection of non-Markovian faults and negligible hardware overhead (<0.1% FPGA resources, O(d) scaling). The SDM reframes fault tolerance from continuous local correction to interventionist safety, analogous to circuit breakers in classical control systems. This work is intended for researchers and engineers in quantum error correction, quantum control hardware, FPGA-based systems, and fault-tolerant quantum architectures, and is presented as an engineering and information-theoretic contribution, not a proposal of new physical laws.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Abstract Long-run quantum execution remains fundamentally constrained, not primarily by gate infidelity, but by cumulative instability of the rotating phase reference during runtime. While contemporary quantum control stacks rely on calibration, dynamical decoupling, and quantum error correction, these mechanisms operate reactively and assume that the underlying phase frame remains valid between interventions. This assumption breaks down as execution depth, runtime, and system size increase. This note reframes long-run execution failure as a phase-frame stability problem rather than a post-fault correction problem. Using empirical hardware-adjacent observations, it shows that longitudinal drift is structured, temporally correlated, and often collective across qubits, placing it outside the effective bandwidth of fast-noise suppression techniques. As a result, computation is frequently admitted under metastable conditions in which logical error amplification occurs despite unchanged physical gate metrics. Based on this empirical and structural analysis, the note identifies a missing architectural element: a preventive drift-bounding layer that constrains phase-frame deviation before execution proceeds. The argument is intentionally architectural rather than implementational. No hardware-specific parameters, algorithms, or corrective primitives are disclosed. The purpose of this document is to establish why scalable quantum execution requires preventive phase stabilization at the execution boundary, and why reactive correction alone cannot remove this limitation. Detailed theoretical foundations, validation pathways, and hardware-compatible realizations exist but are intentionally excluded from this public note.
The design of quantum hardware that reduces and mitigates errors is essential for practical quantum error correction (QEC) and useful quantum computation. To this end, we introduce the circuit-Quantum Electrodynamics (QED) dual-rail qubit in which our physical qubit is encoded in the single-photon subspace, [Formula: see text], of two superconducting microwave cavities. The dominant photon loss errors can be detected and converted into erasure errors, which are in general much easier to correct. In contrast to linear optics, a circuit-QED implementation of the dual-rail code offers unique capabilities. Using just one additional transmon ancilla per dual-rail qubit, we describe how to perform a gate-based set of universal operations that includes state preparation, logical readout, and parametrizable single and two-qubit gates. Moreover, first-order hardware errors in the cavities and the transmon can be detected and converted to erasure errors in all operations, leaving background Pauli errors that are orders of magnitude smaller. Hence, the dual-rail cavity qubit exhibits a favorable hierarchy of error rates and is expected to perform well below the relevant QEC thresholds with today's coherence times.
Amplitude damping is a dominant source of error in high performance quantum processors. A promising approach in quantum error correction is erasure error conversion, where errors are converted into detectable leakage states. Dual-rail encoding has been shown as a candidate for the conversion of amplitude-damping errors; with unique sensitivities to noise and decoherence sources. Here we present a dual-rail encoding within a single fixed-frequency superconducting multimode transmon qubit. The three island, two junction device comprises two transmonlike modes with a detuning of 0.75-1 GHz, in a coaxial circuit QED architecture. We show the logical bit-flip and phase-flip error rates are more than one order of magnitude lower than the physical error rates, and demonstrate stability and repeatability of the architecture through an extended measurement of three such devices. Finally, we discuss how the error-detected subspace can be used for investigations into the fundamentals of noise and decoherence in fixed-frequency transmon qubits.
Correlated and non-Markovian noise can defeat stabilizer-code performance even when average error rates are low. We propose QEC-C III, a correlation-adaptive hybrid protocol that filters collective dephasing components via an inner dual-rail decoherence-free subspace (DFS) and corrects residual local faults with an outer stabilizer code. To interface DFS mismatch with the outer code in a measurable way, we derive a per-round encoded dephasing probability pZ L (∆t) in terms of experimentally accessible quantities, enabling direct calibration by encoded Ramsey/echo experiments. We introduce a renewal-gated syndrome protocol that segments data into syndrome-defined epochs; under a regenerative assumption it yields a consistent estimator of a per-round logical failure rate and supplies practical diagnostics when the assumption breaks. Finally, we provide a DFS-preserving railsymmetrization primitive that averages rail-dependent coherent errors during parity-check extraction. HEOM simulations validate DFS invariance under strongly non-Markovian collective dephasing and quantify robustness under controlled symmetry breaking.