Description This work introduces the Systolic Drift Monitor (SDM), a universal hardware safety layer designed to address a fundamental limitation in real-time quantum error correction (QEC): the inability of finite-window decoders to detect slow, non-Markovian drift such as 1/f noise. We formalize this limitation as the Lag Horizon, an information-theoretic blind spot arising from finite memory and boundary-only observation. Using the Fisher-Blindness No-Go Theorem, we show that when error correlations extend beyond the decoder window, the Fisher information available to any windowed observer vanishes, rendering structural phase transitions statistically undetectable regardless of processing speed. To resolve this blindness, we propose the SDM as a minimal, architecture-independent hardware primitive that operates alongside—rather than within—the primary decoder. Implemented on 2025-era FPGA platforms (AMD Versal ACAP and Intel Agilex), the SDM performs deterministic, infinite-horizon integration of syndrome flux, restoring visibility to topological drift while maintaining constant latency. We analyze two experimentally relevant regimes: Superconducting dual-rail qubits, where the SDM functions as an asynchronous drift watchdog for long-timescale flux noise (>100 μs) despite sub-microsecond QEC cycles. Neutral atom processors, where large cycle times (>1 ms) allow the SDM to operate as a hard safety interlock, converting atom loss and leakage precursors into flagged erasures before logical failure. Simulation-based validation across surface codes and color codes demonstrates pre-symptomatic detection of non-Markovian faults and negligible hardware overhead (<0.1% FPGA resources, O(d) scaling). The SDM reframes fault tolerance from continuous local correction to interventionist safety, analogous to circuit breakers in classical control systems. This work is intended for researchers and engineers in quantum error correction, quantum control hardware, FPGA-based systems, and fault-tolerant quantum architectures, and is presented as an engineering and information-theoretic contribution, not a proposal of new physical laws.
Description This work introduces the Systolic Drift Monitor (SDM), a universal hardware safety layer designed to address a fundamental limitation in real-time quantum error correction (QEC): the inability of finite-window decoders to detect slow, non-Markovian drift such as 1/f noise. We formalize this limitation as the Lag Horizon, an information-theoretic blind spot arising from finite memory and boundary-only observation. Using the Fisher-Blindness No-Go Theorem, we show that when error correlations extend beyond the decoder window, the Fisher information available to any windowed observer vanishes, rendering structural phase transitions statistically undetectable regardless of processing speed. To resolve this blindness, we propose the SDM as a minimal, architecture-independent hardware primitive that operates alongside—rather than within—the primary decoder. Implemented on 2025-era FPGA platforms (AMD Versal ACAP and Intel Agilex), the SDM performs deterministic, infinite-horizon integration of syndrome flux, restoring visibility to topological drift while maintaining constant latency. We analyze two experimentally relevant regimes: Superconducting dual-rail qubits, where the SDM functions as an asynchronous drift watchdog for long-timescale flux noise (>100 μs) despite sub-microsecond QEC cycles. Neutral atom processors, where large cycle times (>1 ms) allow the SDM to operate as a hard safety interlock, converting atom loss and leakage precursors into flagged erasures before logical failure. Simulation-based validation across surface codes and color codes demonstrates pre-symptomatic detection of non-Markovian faults and negligible hardware overhead (<0.1% FPGA resources, O(d) scaling). The SDM reframes fault tolerance from continuous local correction to interventionist safety, analogous to circuit breakers in classical control systems. This work is intended for researchers and engineers in quantum error correction, quantum control hardware, FPGA-based systems, and fault-tolerant quantum architectures, and is presented as an engineering and information-theoretic contribution, not a proposal of new physical laws.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Description / Abstract Abstract Current Quantum Error Correction (QEC) protocols, such as the Surface Code, are typically optimized for Markovian noise models where errors are independent and identically distributed. We demonstrate that superconducting qubit architectures are susceptible to a specific class of non-Markovian correlated drift that remains undetectable by standard stabilizer measurements until it induces a catastrophic coherence collapse. We analytically derive this failure mode as a Fisher Information Horizon Limit, proving that an estimator optimizing solely for instantaneous gate fidelity experiences a divergence in variance regarding long-term structural drift. We model this "Hyper-Stable" regime as a system approaching an Exceptional Point (EP) in its effective non-Hermitian Hamiltonian. To mitigate this, we propose a control architecture utilizing a Systolic Drift Monitor (SDM) that integrates the geometric Berry phase of the noise history. By implementing a periodic Frame Update Unitary (conceptually isomorphic to basis rotation) on a dual-rail encoded subspace, we convert latent non-Markovian drift into observable execution variance, allowing for real-time suppression of the spectral singularity. Implementation Details The proposed architecture is designed for deployment on FPGA-based quantum control stacks (e.g., Xilinx RFSoC). Simulation results demonstrate a significant improvement in effective coherence times under 1/{f^alpha} noise conditions (alpha = 0.95) by preventing the system from entering the null space of the stabilizer code. The hardware logic is estimated to operate with a feedback latency of < 200 ns, well within the coherence time of standard transmon qubits. Keywords Quantum Error Correction, Superconducting Qubits, Non-Markovian Noise, Exceptional Points, Non-Hermitian Physics, FPGA Control, Dual-Rail Encoding, Fisher Information, Cramér-Rao Bound, Control Theory, Systolic Drift Monitor
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration.
To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits.
Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
This review synthesizes current understanding of decoherence pathways across leading hardware platforms and explains why several experimentally observed noise features—drift, burst events, coherent components, correlated and non-Markovian structure, and leakage—can be disproportionately damaging for QEC. Decoherence remains the dominant impediment to scalable quantum computing because it is not a single error mechanism but a system-level phenomenon arising from materials defects, electromagnetic loss, control electronics, measurement backaction, and the broader environment in which a processor operates. Quantum error correction (QEC) is designed to algorithmically suppress physical noise, yet its practical success depends on how closely real devices satisfy the assumptions under which fault tolerance is proved: approximate locality, weak temporal correlations, sufficiently stochastic error statistics, low leakage, and reliable syndrome extraction. We then evaluate fundamental and engineering challenges that shape the viability of QEC at scale: syndrome measurement fidelity, correlated error suppression, decoding latency and classical co-processing, architectural constraints (connectivity, crosstalk, calibration overhead), and the resource cost of implementing a universal fault-tolerant gate set. Recent demonstrations of below-threshold behaviour and “break-even” regimes show that QEC is transitioning from theory to practice, but also clarify what remains unresolved: maintaining stable noise below fault-tolerance targets over long times, scaling to many logical qubits with low correlated-error rates, and integrating hardware-aware codes and decoders. We conclude with research priorities that treat decoherence and QEC as part of a co-designed stack spanning device physics, control, architecture, and algorithms.
Surface--code threshold theorems traditionally assume an abstract local noise model, typically an i.i.d.\ or weakly correlated Pauli channel on a flat hardware lattice, and establish exponential suppression of logical error below a critical physical error rate~\cite{dennis2002topological,aharonov2008fault,aliferis2006quantum,fowler2012surface,terhal2015quantum}. In this setting the surface code functions primarily as a quantum memory architecture, with fault--tolerant computation obtained by supplementing the code with transversal gates and magic--state distillation under the same phenomenological noise assumptions~\cite{nielsen2010quantum,watrous2018theory}. Such analyses, however, do not natively accommodate curved or slowly drifting chronogeometries, structured vacuum or spectral noise, or process--level equivalence between distinct QEC schedules. This work develops a triadic--Fourfold fault--tolerance framework for surface--code quantum computation in the IQR/PQS setting of~\cite{Borom:2025chrono}. The starting point is a full fourfold inter--modal correlator G^Λ and its ideal counterpart G^Λ0, defined on a QEC diagnostic realized reference configuration and a QEC--realized weave equipped with a Good--clock C=(T^,Ut). The associated noise kernel ΔG^ is required to lie in a Triadic--Fourfold Noise Class Ntri-4F with correlational, vacuum, and spectral sectors satisfying suitable clustering and time--scale separation conditions~\cite{breuer2002theory,riera2012thermal}. From this data the analysis extracts triad--split local error rates (pcorr,pvac,pspec), triad--resolved leakage parameters εps(a), and process differentials δa as explicit functionals of ΔG^. The main Triadic--Fourfold Threshold Theorem shows that the \emph{standard} surface--code family on the emergent Twofold register still exhibits an exponential logical threshold controlled by the correlational error rate pcorr, while vacuum and spectral contributions appear only through small, explicitly quantified correction terms fvac,fspec. At the same time, a triadic process threshold bound ensures that, provided the global process differential δtot is sufficiently small, all QEC schedules implementing a given logical circuit are holosymmetrically equivalent in the dual--history sense up to a prescribed accuracy. In particular, the noise may arise from a non--Markovian environment, understood here as an environment whose full dynamics is not memoryless or semigroup--like, but whose fast component can still be isolated and treated in a Markovian way for threshold purposes, with the slow, history--carrying components systematically accounted for by the triadic decomposition rather than being ignored. The result is therefore not a new code, but a strictly more general and physically faithful threshold theorem for the usual surface--code architecture: it remains valid in curved, slowly drifting, non--Markovian environments, is formulated directly in terms of field--theoretic correlators, and simultaneously controls both logical correctness and process--level robustness of the computation.
Quantum error correction (QEC) is the most promising route toward fault-tolerant quantum computing and, thus, useful quantum computers. QEC operates as a continuous measure-decode-correct cycle: ancilla qubits are read out, a decoder infers errors from the resulting syndromes, and corrections are applied before the next round begins. Within this loop, readout occupies a uniquely critical role, as it is the sole source of ground truth available to the decoder. Yet readout is also the slowest and most error-prone operation in the stack, with characteristics that vary across qubits and drift over time; This complexity propagates directly to the classical control hardware, and in particular to the FPGA-hosted machine-learning (ML) discriminator that must classify each analog signal into a binary syndrome outcome. Despite this central role, QEC performance has not yet been studied in depth from the perspective of readout characteristics, readout length, and their co-design with an ML discriminator.
We introduce Oraqle, an end-to-end benchmarking framework that evaluates qubit-state readout and its impact on QEC performance across real experimentally extracted qubit-state-readout datasets, state-of-the-art ML discriminators, multiple QEC codes, and hardware regimes spanning current to projected devices. Our study reveals three asymmetric findings: The measurement duration can be significantly reduced with nearly no penalty to the logical error rate; The discriminator complexity barely affects the QEC performance, as residual errors are written into device physics rather than the model; and the impact of qubit-state readout on the logical error rate is conditional on where the hardware sits in the QEC landscape, a window that widens as devices mature.