Especially in noisy intermediate-scale quantum (NISQ) devices, fault-tolerant quantum computing cannot be realized without quantum error correction. High error rates in quantum systems stemming from decoherence and gate defects call for effective and flexible QEC systems. This paper presents a novel FPGA-based architecture using dynamic reconfiguration to maximize hardware resources in response to real-time error patterns. Supporting bit-flip, phase-flip, and depolarizing faults among several error correction techniques guarantees high accuracy and little hardware overhead. Scaled for surface code distances up to and beyond, the design combines modular pipelines, adaptive hardware allocation, and error pattern detection. Designed on a Xilinx XC7A50T-CPG236 FPGA, the system showed notable gains over static architecture, averaging 30% lower latency and 20% less resource use overall. Low latency and high throughput are maintained while this dynamic technique enables flexible adaptability to several quantum error models. The outcomes show how well this structure may improve quantum error-correcting systems and enable the incorporation of QEC into useful quantum computer configurations.
Especially in noisy intermediate-scale quantum (NISQ) devices, fault-tolerant quantum computing cannot be realized without quantum error correction. High error rates in quantum systems stemming from decoherence and gate defects call for effective and flexible QEC systems. This paper presents a novel FPGA-based architecture using dynamic reconfiguration to maximize hardware resources in response to real-time error patterns. Supporting bit-flip, phase-flip, and depolarizing faults among several error correction techniques guarantees high accuracy and little hardware overhead. Scaled for surface code distances up to and beyond, the design combines modular pipelines, adaptive hardware allocation, and error pattern detection. Designed on a Xilinx XC7A50T-CPG236 FPGA, the system showed notable gains over static architecture, averaging 30% lower latency and 20% less resource use overall. Low latency and high throughput are maintained while this dynamic technique enables flexible adaptability to several quantum error models. The outcomes show how well this structure may improve quantum error-correcting systems and enable the incorporation of QEC into useful quantum computer configurations.
Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum Computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits.In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6×10−10for physical error rate of 10−3) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architecture across multiple decoding units. Our proposed Conjoined-Decoder Architecture (CDA) reduces the storage overhead by 70% (10MB to 2.8MB). Finally, we reduce the bandwidth overheads required to transmit syndromes from the qubits to the decoders by exploiting the sparsity in the syndromes and compressing the data. Our proposed Syndrome Compression reduces the bandwidth requirement by 30x, on an average.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration.
To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits.
Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Quantum error correction (QEC) is indispensable for fault-tolerant quantum computing, yet implementing powerful decoders in hardware remains a bottleneck. Classical algorithms like Minimum Weight Perfect Matching (MWPM) achieve excellent performance but have the problems such as high latency and resource demands, while many emerging machine learning (ML) based decoders either neglect quantization effects or rely on deep networks that exceed practical FPGA budgets. In this work, we present QUNET, a quantized modular UNet decoder for surface codes, which incorporates quantization-aware training (QAT) to compress weights and activations to as low as 4 bits and introduces an early-exit mechanism that dynamically routes simple syndromes through a shallower subnetwork to save on average 34% of decoding time. Our design achieves competitive logical accuracy compared to MWPM, while consuming up to 50% fewer FPGA resources than dataflow implementations, demonstrating a practical hardware deployment of QEC decoders that provide great flexibility and efficiency. The modularity of our design also ensures high scalability, allowing the creation of deeper networks without additional hardware overhead.
Reliable large-scale quantum computation relies on fault-tolerant architectures, where quantum error correction (QEC) continuously extracts and decodes error syndromes in real time. A critical component in QEC is the decoder, a classical subsystem that must simultaneously deliver high logical accuracy and ultra-low latency. This paper presents a novel algorithm-hardware co-design that improves the accuracy-latency trade-off over existing approaches such as vanilla Minimum-Weight Perfect Matching (MWPM) and Union-Find (UF) decoders. At the algorithmic level, we introduce coset ensemble decoding, which improves UF decoding by explicitly exploiting logically equivalent cosets. Our method performs ensemble forest exploration to generate multiple coset-consistent candidates and aggregates them to approximate coset-level maximum-likelihood decoding. We further reduce computational and memory complexity via reverse-order elimination and lossless graph compression, without sacrificing accuracy. At the hardware level, we design a domain-specific architecture that temporally reuses resources, avoiding the code-distance-proportional resource growth in prior spatial architectures. Several optimizations, such as multi-bank memory hashing and hierarchical ID mapping, are proposed to mitigate pipeline stalls and memory conflicts under highly concurrent access patterns. Under a circuit-level depolarizing noise model, our co-design approach achieves a better accuracy-latency trade-off than prior MWPM- and UF-based decoders, while reducing FPGA LUT consumption by up to 8.2 times compared with reported UF-based decoder resources. The tunable candidate number further exposes a flexible design knob, enabling users to tailor decoding performance to the requirements of different fault-tolerant workloads. Our implementation is publicly available at https://github.com/IMSeonL/coset-ensemble-decoder.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Quantum error correction (QEC) represents the cornerstone technology for realizing fault-tolerant quantum computing, addressing the fundamental challenge of quantum state decoherence in noisy intermediate-scale quantum (NISQ) devices. This comprehensive review examines recent advances in QEC implementations from 2020-2024, spanning theoretical foundations to practical hardware demonstrations. We analyze the evolution from pioneering stabilizer codes to modern topological approaches, with particular emphasis on surface codes and low-density parity-check (LDPC) codes that have demonstrated below-threshold error correction in superconducting and trapped-ion systems. The paper provides a comparative analysis of classical and machine learning-based decoder algorithms, evaluating their performance through complexity analysis and threshold comparisons in real-time error correction scenarios. Through examination of breakthrough experiments by Google, IBM, Quantinuum, and emerging platforms, we assess the current state of fault-tolerant quantum computing and identify critical engineering challenges including correlated noise models, cryogenic control systems, and scalable logical gate implementations. Our quantitative analysis reveals that while significant progress has been made toward practical fault-tolerance thresholds, achieving the resource efficiency and reliability required for large-scale quantum computation remains challenging. We provide detailed resource estimates for key applications including Shor's algorithm and optimization problems, along with analysis of industry roadmaps toward thousand-logical-qubit systems. This review serves as a comprehensive guide for researchers and engineers working toward the next generation of fault-tolerant quantum computers, with particular focus on information-theoretic perspectives relevant to quantum information entropy and syndrome processing.