Quantum error correction (QEC) is indispensable for fault-tolerant quantum computing, yet implementing powerful decoders in hardware remains a bottleneck. Classical algorithms like Minimum Weight Perfect Matching (MWPM) achieve excellent performance but have the problems such as high latency and resource demands, while many emerging machine learning (ML) based decoders either neglect quantization effects or rely on deep networks that exceed practical FPGA budgets. In this work, we present QUNET, a quantized modular UNet decoder for surface codes, which incorporates quantization-aware training (QAT) to compress weights and activations to as low as 4 bits and introduces an early-exit mechanism that dynamically routes simple syndromes through a shallower subnetwork to save on average 34% of decoding time. Our design achieves competitive logical accuracy compared to MWPM, while consuming up to 50% fewer FPGA resources than dataflow implementations, demonstrating a practical hardware deployment of QEC decoders that provide great flexibility and efficiency. The modularity of our design also ensures high scalability, allowing the creation of deeper networks without additional hardware overhead.
Quantum error correction (QEC) is indispensable for fault-tolerant quantum computing, yet implementing powerful decoders in hardware remains a bottleneck. Classical algorithms like Minimum Weight Perfect Matching (MWPM) achieve excellent performance but have the problems such as high latency and resource demands, while many emerging machine learning (ML) based decoders either neglect quantization effects or rely on deep networks that exceed practical FPGA budgets. In this work, we present QUNET, a quantized modular UNet decoder for surface codes, which incorporates quantization-aware training (QAT) to compress weights and activations to as low as 4 bits and introduces an early-exit mechanism that dynamically routes simple syndromes through a shallower subnetwork to save on average 34% of decoding time. Our design achieves competitive logical accuracy compared to MWPM, while consuming up to 50% fewer FPGA resources than dataflow implementations, demonstrating a practical hardware deployment of QEC decoders that provide great flexibility and efficiency. The modularity of our design also ensures high scalability, allowing the creation of deeper networks without additional hardware overhead.
Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by 3.1× and 6.5×. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate p=10−3, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at 1μs average latency, and by 13% under a strict 1μs deadline.
Quantum error-correcting codes (QECCs) can eliminate the negative effects of quantum noise, the major obstacle to the execution of quantum algorithms. However, realizing practical quantum error correction (QEC) requires resolving many challenges to implement a high-performance real-time decoding system. Many decoding algorithms have been proposed and optimized in the past few decades, of which neural network (NNs) based solutions have drawn an increasing amount of attention due to their high efficiency. Unfortunately, previous works on neural decoders are still at an early stage and have only relatively simple architectures, which makes them unsuitable for practical QEC. In this work, we propose a scalable, fast, and programmable neural decoding system to meet the requirements of FTQEC for rotated surface codes (RSC). Firstly, we propose a hardware-efficient NN decoding algorithm with relatively low complexity and high accuracy. Secondly, we develop a customized hardware decoder with architectural optimizations to reduce latency. Thirdly, our proposed programmable architecture boosts the scalability and flexibility of the decoder by maximizing parallelism. Fourthly, we build an FPGA-based decoding system with integrated control hardware for evaluation. Our L=5 (L is the code distance) decoder achieves an extremely low decoding latency of 197 ns, and the L=7 configuration also requires only 1.136 μs, both taking 2L rounds of syndrome measurements. The accuracy results of our system are close to minimum weight perfect matching (MWPM). Furthermore, our programmable architecture reduces hardware resource consumption by up to 3.0× with only a small latency loss. We validated our approach in real-world scenarios by conducting a proof-of-concept benchmark with practical noise models, including one derived from experimental data gathered from physical hardware.
Reliable large-scale quantum computation relies on fault-tolerant architectures, where quantum error correction (QEC) continuously extracts and decodes error syndromes in real time. A critical component in QEC is the decoder, a classical subsystem that must simultaneously deliver high logical accuracy and ultra-low latency. This paper presents a novel algorithm-hardware co-design that improves the accuracy-latency trade-off over existing approaches such as vanilla Minimum-Weight Perfect Matching (MWPM) and Union-Find (UF) decoders. At the algorithmic level, we introduce coset ensemble decoding, which improves UF decoding by explicitly exploiting logically equivalent cosets. Our method performs ensemble forest exploration to generate multiple coset-consistent candidates and aggregates them to approximate coset-level maximum-likelihood decoding. We further reduce computational and memory complexity via reverse-order elimination and lossless graph compression, without sacrificing accuracy. At the hardware level, we design a domain-specific architecture that temporally reuses resources, avoiding the code-distance-proportional resource growth in prior spatial architectures. Several optimizations, such as multi-bank memory hashing and hierarchical ID mapping, are proposed to mitigate pipeline stalls and memory conflicts under highly concurrent access patterns. Under a circuit-level depolarizing noise model, our co-design approach achieves a better accuracy-latency trade-off than prior MWPM- and UF-based decoders, while reducing FPGA LUT consumption by up to 8.2 times compared with reported UF-based decoder resources. The tunable candidate number further exposes a flexible design knob, enabling users to tailor decoding performance to the requirements of different fault-tolerant workloads. Our implementation is publicly available at https://github.com/IMSeonL/coset-ensemble-decoder.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Fault-tolerant quantum computation critically depends on the ability to detect and correct physical qubit errors faster than they accumulate. The surface code (SC) has emerged as the most experimentally promising quantum error correction (QEC) framework due to its high threshold and local stabilizer structure, yet its practical performance is bottlenecked by decoder efficiency. Traditional decoding approaches such as minimum-weight perfect matching (MWPM) achieve near-optimal accuracy under independent noise but struggle with correlated errors, circuit-level noise, and real-time latency constraints. This paper investigates how neural network (NN)-based decoders reduce logical error rates in SC quantum systems by learning complex syndrome-to-correction mappings from data. We propose a hybrid convolutional-recurrent neural architecture that processes stabilizer measurement syndromes across both spatial and temporal dimensions, enabling the decoder to capture correlated error patterns inherent in realistic hardware. Systematic simulations under depolarizing, biased, and circuit-level noise models demonstrate that the proposed neural decoder achieves a logical error rate reduction of up to 41.3% compared to MWPM at a physical error rate of p = 0.008, while maintaining sub-millisecond decoding latency compatible with superconducting qubit cycle times. These results establish that data-driven neural decoders represent a scalable and hardware-compatible pathway toward achieving the logical error rates required for practical fault-tolerant quantum computing.
Real-time decoding is a major bottleneck in scaling quantum error correction (QEC) from noisy intermediate-scale quantum (NISQ) devices to fault-tolerant quantum computing. We present an adaptive confidence-gated decoding framework for the rotated surface code that treats decoding as a two-stage inference problem. A lightweight feed-forward neural network performs fast-path decoding for the majority of syndrome measurements, while only low-confidence predictions are escalated to a minimum-weight perfect matching (MWPM) refinement stage. We benchmark the framework on rotated surface codes with distances d∈{3,5,7,9,11} under circuit-level depolarising noise using the Stim stabiliser simulator. The evaluation characterises logical accuracy, confidence-controlled accuracy-latency trade-offs, decoding throughput, per-shot latency, and decoding-graph resource scaling. Routing only 3.3%-6.2% of syndromes to the refinement stage improves logical accuracy from 99.21% for the neural-only baseline to 99.81% at a confidence threshold of 0.95 while incurring only a bounded increase in average decoding cost. Neural-decoder throughput saturates near 4.6×105 samples s−1 at batch size 512 on commodity CPU hardware, indicating that the neural fast path is not the dominant throughput bottleneck beyond code distance d=7. We release the complete benchmarking pipeline, trained models, raw benchmark data, and source code, and explicitly distinguish the experimentally validated contributions from the broader hardware-aware QEC co-design roadmap, including hardware-constrained code discovery, GPU-accelerated inference, and multi-noise optimisation, which remain directions for future work.