While Bose-Chaudhari-Hocquenghem (BCH) codes excel at short block lengths, structural innovations enable Low-Density Parity-Check (LDPC) codes to outperform them. This paper presents three key advancements through systematic construction of scalable full-rank parity-check matrices: [1] Customized (15,10) LDPC protograph code achieves coding gain of 2.5 dB and 1 dB over the (15,11) and (15,7) BCH codes, respectively, at 10⁻⁴ BER. (2) Pruning and Girth optimization provide an additional 0.5 dB gain; reduce Tanner graph edges by 20 % and effectively suppress the error floor by preserving the minimum distance. (3) Protographs enable flexible, parametrized code construction. The proposed (120,80) LDPC code demonstrates performance comparable to the CCSDS (128,64) LDPC code under standard iterative decoding. Unlike neural decoders that face scalability limitations, the new approach supports dynamic, architecturally stable FPGA implementations across various code lengths. The results establish new benchmarks for short-length LDPC codes, thereby achieving 3.0 dB SNR at BER 10⁻², and outperforming both traditional BCH and 5G NR transformer decoders. This work bridges the gap between theoretical optimization and practical deployment for emerging 6G machine-type communications. Finally, microcontroller-based hardware validation shows a 10 % improvement in error correction for a free-space optical communication link.
While Bose-Chaudhari-Hocquenghem (BCH) codes excel at short block lengths, structural innovations enable Low-Density Parity-Check (LDPC) codes to outperform them. This paper presents three key advancements through systematic construction of scalable full-rank parity-check matrices: [1] Customized (15,10) LDPC protograph code achieves coding gain of 2.5 dB and 1 dB over the (15,11) and (15,7) BCH codes, respectively, at 10⁻⁴ BER. (2) Pruning and Girth optimization provide an additional 0.5 dB gain; reduce Tanner graph edges by 20 % and effectively suppress the error floor by preserving the minimum distance. (3) Protographs enable flexible, parametrized code construction. The proposed (120,80) LDPC code demonstrates performance comparable to the CCSDS (128,64) LDPC code under standard iterative decoding. Unlike neural decoders that face scalability limitations, the new approach supports dynamic, architecturally stable FPGA implementations across various code lengths. The results establish new benchmarks for short-length LDPC codes, thereby achieving 3.0 dB SNR at BER 10⁻², and outperforming both traditional BCH and 5G NR transformer decoders. This work bridges the gap between theoretical optimization and practical deployment for emerging 6G machine-type communications. Finally, microcontroller-based hardware validation shows a 10 % improvement in error correction for a free-space optical communication link.
This paper,based on algebra and graph,proposes a method for constructing structured low-density parity-check(LDPC) codes.In this method,the authors design a connected graph with three kinds of special path to ensure that the Tanner graph of the parity check matrix mapped from the connected graph is without short cycles.The construction method results in two classes of(3,k)-regular quasi-cyclic LDPC codes with girth 8 and 12 respectively.Furthermore,by extending this construction method,two classes of LDPC codes with column weight 2,whose girths are respectively 16 and 24,can be obtained.The simulation studies show that these codes can achieve better performance than randomly constructed regular LDPC codes over AWGN channels with iterative decoding.At the BER of 10-5,the new proposed(3,6)-regular(4356,2205) QC-LDPC code performs 1.48dB from the Shannon limit.Moreover,it outperforms the random regular LDPC code of comparable parameters by 0.1dB.For the new proposed structured LDPC codes with column weight 2,they can achieve about 2dB coding gains with respect to the random regular LDPC codes with similar block lengths and code rates.
In this paper we propose an innovative LDPC coded modulation scheme. We design binary low density parity check (LDPC) codes that are combined with high level modulations such as 8PSK and 16QAM with and without a channel interleaver. At the receiver a demapper transforms the received inphase and quadrature samples to produce reliability information that feeds the binary LDPC decoder. Using this scheme, the same encoder and decoder can support various modulations. Analysis of ensemble average weight enumerators shows that the minimum distance of the proposed LDPC codes grows linearly with block size. Our constructions are based on protograph structures that support high-speed decoder implementations. We also show that precoding can be used to lower the threshold of LDPC codes. The decoding thresholds of the proposed codes, which have linearly increasing minimum distance in block size, outperform that of regular LDPC codes. Furthermore, a family of low to high rate codes, with thresholds that adhere closely to their respective channel capacity thresholds, is presented. For maximum variable node degree 6, the iterative decoding thresholds of these codes outperform the best known unstructured irregular LDPC codes reported in the literature. Iterative decoding simulation results are provided for BPSK, QPSK, 8PSK, and 16QAM modulations over the additive white Gaussian noise channel. FPGA simulation results for the proposed LDPC codes with input block size of 4096 and QPSK modulation (throughput=1 bps/Hz) show that a frame error rate of 10-8and a bit error rate of 10-10can be achieved at Eb/No=1.50 dB
Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. \nThis thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. \nRow-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. \nQuasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. \nDecoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing \nthe starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. \nTechniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.
Low Density Parity Check (LDPC) codes over nonbinary Galois Fields GF(q) are a generalization of the industrial standard binary LDPC codes for forward error correction in communication and information systems.The nonbinary codes can achieve significantly better performance for short and moderate block lengths.A lot of works concerning "good" LDPC codes parity check matrix construction has been published so far.However, it is well known that efficient partially parallel hardware decoder architectures are allowed only for codes with blockwise partitioned structure of the parity check matrix, called structured codes.In this paper we present a versatile algorithm for construction of codes that are both nonbinary and structured.The proposed algorithm aims at optimizing the code graph (Tanner graph) by reducing the existence of small cycles with low external connectivity, while at the same time selecting appropriate nonzero coefficients from the Galois Field under interest.The algorithm can be used for code construction of any field order, block length and code rate.
Belief-propagation (BP) decoding of short and moderate-length low-density parity-check (LDPC) codes is limited by finite-length graph effects: a single decoder trajectory can become trapped or oscillatory even when an alternative trajectory would decode the received word. Existing ensemble-BP decoders create the required diversity through multiple parity-check matrices, automorphisms, modified schedules, subcodes, or altered update rules. We introduce row-boosted ensemble (RBE) decoding as a minimal decoder-side diversity mechanism: all ensemble members share the same parity-check matrix and the same BP kernel, and differ only in a small set of parity-check rows whose outgoing messages are boosted. On the 5G~NR BG1 (144,96) code, RBE with 32 members lowers the frame-error rate of BP with 20 iterations (BP-20) from 1.6×10−2 to 1.6×10−3 at Eb/N0=4.0dB, outperforming saturated-min-sum and affine subcode ensembles of equal size. Increasing the ensemble size yields additional gains, indicating that RBE provides a scalable performance-complexity tradeoff. The gains transfer across 5G~NR block lengths and rates, to non-5G short LDPC codes, and across flooding and layered schedules.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area.
This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.