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IEEE Military Communications Conference (MILCOM)

Protograph Based Low Error Floor LDPC Coded Modulation

D. Divsalar, C. Jones

Published Mar 22, 2006• 36 citations
Publisher

Abstract

In this paper we propose an innovative LDPC coded modulation scheme. We design binary low density parity check (LDPC) codes that are combined with high level modulations such as 8PSK and 16QAM with and without a channel interleaver. At the receiver a demapper transforms the received inphase and quadrature samples to produce reliability information that feeds the binary LDPC decoder. Using this scheme, the same encoder and decoder can support various modulations. Analysis of ensemble average weight enumerators shows that the minimum distance of the proposed LDPC codes grows linearly with block size. Our constructions are based on protograph structures that support high-speed decoder implementations. We also show that precoding can be used to lower the threshold of LDPC codes. The decoding thresholds of the proposed codes, which have linearly increasing minimum distance in block size, outperform that of regular LDPC codes. Furthermore, a family of low to high rate codes, with thresholds that adhere closely to their respective channel capacity thresholds, is presented. For maximum variable node degree 6, the iterative decoding thresholds of these codes outperform the best known unstructured irregular LDPC codes reported in the literature. Iterative decoding simulation results are provided for BPSK, QPSK, 8PSK, and 16QAM modulations over the additive white Gaussian noise channel. FPGA simulation results for the proposed LDPC codes with input block size of 4096 and QPSK modulation (throughput=1 bps/Hz) show that a frame error rate of 10-8and a bit error rate of 10-10can be achieved at Eb/No=1.50 dB

DOI
10.1109/milcom.2005.1605713

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In this paper we propose an innovative LDPC coded modulation scheme. We design binary low density parity check (LDPC) codes that are combined with high level modulations such as 8PSK and 16QAM with and without a channel interleaver. At the receiver a demapper transforms the received inphase and quadrature samples to produce reliability information that feeds the binary LDPC decoder. Using this scheme, the same encoder and decoder can support various modulations. Analysis of ensemble average weight enumerators shows that the minimum distance of the proposed LDPC codes grows linearly with block size. Our constructions are based on protograph structures that support high-speed decoder implementations. We also show that precoding can be used to lower the threshold of LDPC codes. The decoding thresholds of the proposed codes, which have linearly increasing minimum distance in block size, outperform that of regular LDPC codes. Furthermore, a family of low to high rate codes, with thresholds that adhere closely to their respective channel capacity thresholds, is presented. For maximum variable node degree 6, the iterative decoding thresholds of these codes outperform the best known unstructured irregular LDPC codes reported in the literature. Iterative decoding simulation results are provided for BPSK, QPSK, 8PSK, and 16QAM modulations over the additive white Gaussian noise channel. FPGA simulation results for the proposed LDPC codes with input block size of 4096 and QPSK modulation (throughput=1 bps/Hz) show that a frame error rate of 10-8and a bit error rate of 10-10can be achieved at Eb/No=1.50 dB
We propose several LDPC code constructions that simultaneously achieve good threshold and error floor performance. Minimum distance is shown to grow linearly with block size (similar to regular codes of variable degree at least 3) by considering ensemble average weight enumerators. Our constructions are based on projected graph, or protograph, structures that support high-speed decoder implementations. As with irregular ensembles, our constructions are sensitive to the proportion of degree-2 variable nodes. A code with too few such nodes tends to have an iterative decoding threshold that is far from the capacity threshold. A code with too many such nodes tends to not exhibit a minimum distance that grows linearly in block length. In this paper we also show that preceding can be used to lower the threshold of regular LDPC codes. The decoding thresholds of the proposed codes, which have linearly increasing minimum distance in block size, outperform that of regular LDPC codes. Furthermore, a family of low to high rate codes, with thresholds that adhere closely to their respective channel capacity thresholds, is presented. Simulation results for a few example codes show that the proposed codes have low error floors as well as good threshold SNR performance.
Low-density parity-check (LDPC) codes characterized by minimum Hamming distances proportional to block sizes have been demonstrated. Like the codes mentioned in the immediately preceding article, the present codes are error-correcting codes suitable for use in a variety of wireless data-communication systems that include noisy channels. The previously mentioned codes have low decoding thresholds and reasonably low error floors. However, the minimum Hamming distances of those codes do not grow linearly with code-block sizes. Codes that have this minimum-distance property exhibit very low error floors. Examples of such codes include regular LDPC codes with variable degrees of at least 3. Unfortunately, the decoding thresholds of regular LDPC codes are high. Hence, there is a need for LDPC codes characterized by both low decoding thresholds and, in order to obtain acceptably low error floors, minimum Hamming distances that are proportional to code-block sizes. The present codes were developed to satisfy this need. The minimum Hamming distances of the present codes have been shown, through consideration of ensemble-average weight enumerators, to be proportional to code block sizes. As in the cases of irregular ensembles, the properties of these codes are sensitive to the proportion of degree-2 variable nodes. A code having too few such nodes tends to have an iterative decoding threshold that is far from the capacity threshold. A code having too many such nodes tends not to exhibit a minimum distance that is proportional to block size. Results of computational simulations have shown that the decoding thresholds of codes of the present type are lower than those of regular LDPC codes. Included in the simulations were a few examples from a family of codes characterized by rates ranging from low to high and by thresholds that adhere closely to their respective channel capacity thresholds; the simulation results from these examples showed that the codes in question have low error floors as well as low decoding thresholds. As an example, the illustration shows the protograph (which represents the blueprint for overall construction) of one proposed code family for code rates greater than or equal to 1.2. Any size LDPC code can be obtained by copying the protograph structure N times, then permuting the edges. The illustration also provides Field Programmable Gate Array (FPGA) hardware performance simulations for this code family. In addition, the illustration provides minimum signal-to-noise ratios (Eb/No) in decibels (decoding thresholds) to achieve zero error rates as the code block size goes to infinity for various code rates. In comparison with the codes mentioned in the preceding article, these codes have slightly higher decoding thresholds.
A construction method for protograph-based LDPC codes that simultaneously achieve low iterative decoding threshold and linear minimum distance is proposed. We start with a high-rate protograph LDPC code with variable node degrees of at least 3. Lower rate codes are obtained by splitting check nodes and connecting them by degree-2 nodes. This guarantees the linear minimum distance property for the lower-rate codes. Excluding checks connected to degree-1 nodes, we show that the number of degree-2 nodes should be at most one less than the number of checks for the protograph LDPC code to have linear minimum distance. Iterative decoding thresholds are obtained by using the reciprocal channel approximation. Thresholds are lowered by using either precoding or at least one very high-degree node in the base protograph. A family of high- to low-rate codes with minimum distance linearly increasing in block size and with capacity-approaching performance thresholds is presented. FPGA simulation results for a few example codes show that the proposed codes perform as predicted
This paper provides a construction method for low-rate low density parity check codes. Inspired by recently proposed accumulate-repeat-accumulate (ARA) codes, and hybrid concatenated codes, in this paper we extend the construction to low rates. Such codes can be viewed as hybrid concatenations of simple modules such as accumulators, repetition codes, differentiators, and punctured single parity check codes. These codes constitute a subclass of LDPC codes with very fast encoder structure. They also have a projected graph or protograph representation that allows for high-speed decoder implementation. Based on density evolution, we show through some examples that low iterative decoding thresholds close to the channel capacity limits can be achieved, as the block size goes to infinity. Iterative decoding simulation results for short blocks are provided for a few examples that show near-capacity performance and very low error floor
Protograph low-density-parity-check (LDPC) codes are considered to design near-capacity low-rate codes over the binary erasure channel and the binary additive white Gaussian noise channel. For protographs with degree-one variable nodes and doubly-generalized LDPC (DGLDPC) codes, conditions are derived to ensure the equality of bit-error threshold and block-error threshold. Using this condition, low-rate codes with block-error threshold close to capacity are designed and shown to have better error rate performance than other existing codes.
Forward error correcting (FEC) codes are used in many communication standards with a wide range of requirements. FEC codes should work close to capacity, achieve low error floors, and have low decoding complexity. In this paper, we propose a novel category of low-density parity-check (LDPC) codes, based on protograph codes with local irregularity. This new code family generalizes conventional protograph-based LDPC codes and is capable of reducing the iterative decoding threshold of the conventional counterpart. We introduce an adapted version of the protograph extrinsic information transfer (PEXIT) algorithm to estimate decoding thresholds on the binaryinput additive white Gaussian noise channel, perform optimizations on the local irregularity, and simulate the performance of some constructed codes.