In recent years, quantum computers have emerged as a disruptive technology capable of solving problems currently intractable for classical systems. Computation is performed using qubits, which exploit quantum properties like superposition and entanglement, and requires them to operate at cryogenic temperatures. As a result, quantum computers are built around cryostats that reach temperatures as low as \qty{10}{\milli\kelvin}. However, to deliver a significant advantage over conventional approaches, quantum computers must increase their qubit count, improve qubit quality, and adopt more sophisticated control and readout architectures. The integration of more complex or improved cryogenic electronics inside the cryostat can enhance the scalability of these systems, and is the topic of this thesis. The primary technology platform used in this work is based on cryogenic InGaAs/InP high-electron-mobility transistors (HEMTs). One objective was the development of cryogenic circuits that enhance the scalability of spin-qubit quantum computers by enabling efficient signal delivery in control and readout paths. To this end, cryogenic multiplexers were demonstrated with threshold voltages as low as \qty{90}{\milli\volt}, subthreshold swing of \qty{5}{\milli\volt\per dec}, and on-off ratio of $10^7$ at \qty{4}{\kelvin}. In addition, a charge-storage array was developed for the local generation of qubit bias signals, using an operation scheme based on pulse trains to program voltage levels on capacitors that can be placed in proximity to qubit gates. A second objective was the fabrication of HEMTs with enhanced performance for use in cryogenic low-noise amplifiers, which are critical for qubit readout. Studies were performed to characterize self-heating, an effect that limits transistor performance at cryogenic temperatures. Moreover HEMTs with improved characteristics were fabricated, which achieved exceptional values in state-of-the-art metrics, including $f_T =$ \qty{622}{\giga\hertz}, $f_{MAX} =$ \qty{733}{\giga\hertz}, and a noise indication factor $\sqrt{I_{DS}} / g_m =$ \qty{0.17}{\sqrt{\volt \cdot \milli\meter / \siemens}} at \qty{4}{\kelvin}. These results represent a new record for the combination of high-frequency and low-noise performance in a cryogenic HEMT. These results establish the InGaAs/InP HEMT technology as a promising platform for the development of cryogenic circuits, and demonstrate its versatility in addressing multiple applications requiring both single-device performance and integration at the circuit level.
In recent years, quantum computers have emerged as a disruptive technology capable of solving problems currently intractable for classical systems. Computation is performed using qubits, which exploit quantum properties like superposition and entanglement, and requires them to operate at cryogenic temperatures. As a result, quantum computers are built around cryostats that reach temperatures as low as \qty{10}{\milli\kelvin}. However, to deliver a significant advantage over conventional approaches, quantum computers must increase their qubit count, improve qubit quality, and adopt more sophisticated control and readout architectures. The integration of more complex or improved cryogenic electronics inside the cryostat can enhance the scalability of these systems, and is the topic of this thesis. The primary technology platform used in this work is based on cryogenic InGaAs/InP high-electron-mobility transistors (HEMTs). One objective was the development of cryogenic circuits that enhance the scalability of spin-qubit quantum computers by enabling efficient signal delivery in control and readout paths. To this end, cryogenic multiplexers were demonstrated with threshold voltages as low as \qty{90}{\milli\volt}, subthreshold swing of \qty{5}{\milli\volt\per dec}, and on-off ratio of 107 at \qty{4}{\kelvin}. In addition, a charge-storage array was developed for the local generation of qubit bias signals, using an operation scheme based on pulse trains to program voltage levels on capacitors that can be placed in proximity to qubit gates. A second objective was the fabrication of HEMTs with enhanced performance for use in cryogenic low-noise amplifiers, which are critical for qubit readout. Studies were performed to characterize self-heating, an effect that limits transistor performance at cryogenic temperatures. Moreover HEMTs with improved characteristics were fabricated, which achieved exceptional values in state-of-the-art metrics, including fT= \qty{622}{\giga\hertz}, fMAX= \qty{733}{\giga\hertz}, and a noise indication factor IDS/gm= \qty{0.17}{\sqrt{\volt \cdot \milli\meter / \siemens}} at \qty{4}{\kelvin}. These results represent a new record for the combination of high-frequency and low-noise performance in a cryogenic HEMT. These results establish the InGaAs/InP HEMT technology as a promising platform for the development of cryogenic circuits, and demonstrate its versatility in addressing multiple applications requiring both single-device performance and integration at the circuit level.
Multiplexed local charge storage, close to quantum processors at cryogenic temperatures could generate a multitude of control signals, for electronics or qubits, in an efficient manner. Such cryogenic electronics require generating quasi-static control signals with small area footprint, low noise, high stability, low power dissipation and, ideally, in a multiplexed fashion to reduce the number of input/outputs. In this work, we integrate capacitors with cryogenic high-electron mobility transistor (HEMT) arrays and demonstrate quasi-static bias generation using gate pulses controlled in time and frequency domains. Multi-channel bias generation is also demonstrated. Operation at 4 K exhibits improved bias signal variability and greatly reduced subthreshold swing, reaching values of ~6 mV/decade. Due to the very low threshold voltage of 80 mV at 4 K and the steep subthreshold swing, these circuits can provide an advantage over the silicon-based complementary metal-oxide-semiconductor equivalents by allowing operation at significantly reduced drive bias in the low output voltage regime <1 V. Together with their high-speed operation, this makes HEMTs an attractive platform for future cryogenic signal generation electronics in quantum computers.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Cryogenic electronics will have a strong impact on our society through applications as Quantum Computing but also, space communication, and high performance computing Quantum computers, for instance, have the potential to radically advance our computational capability and are predicted to strongly impact fields such as medicine, chemistry, science and finance by allowing to solve computational problems that cannot readily be solved by classical computers The hardware implementations of quantum computers rely on various quantum bit (qubit) technologies, such as superconducting qubits, spin qubits and Majorana fermions All of these Qubits require cryogenic temperatures (<4K) to operate efficiently, and need, and restitute Analog-RF signals for their manipulation, and results respectively Thus, there is a need for cryogenic electronics with a large array of functionalities, operating under extremely low noise conditions with limited power budgets Achieving this will require enhanced understanding of existing transistor technologies, 3D integrated systems and novel nanoelectronic devices employing unique low-temperature effects With these new devices, new ultra-low noise, ultra-low power, and wide-band circuits and systems are emerging, preparing the next computing revolution In this Workshop we will explore state of art status of Quantum computing applications and their associated technology and circuits analog-RF platforms
Engineering research in quantum computing is geared towards building a ”useful” quantum computer; usefulness here refers to the capability of solving computation problems that hold significant value in commercial applications, but are currently impossible to do in reasonable time-frames using classical algorithms. This is fundamentally a problem of scale – problems that can be solved by few-qubit processors can also be readily simulated by classical supercomputers in realistic time-frames, but as these problems grow in complexity, quantum computers are believed to be able to provide an exponential speedup over their classical counterparts, the so-called quantum advantage. However, scaling quantum computers presents many challenges due to the need to perform complex signal control and data processing at nanosecond time scales on fragile quantum systems that need stringent degrees of isolation from the environment for the computations to be carried out with high fidelity. Some of the most promising implementations of experimental-grade quantum computers are maintained in cryogenic environments due to the fact that at low enough temperatures noise processes due to random thermal excitations can be minimized. However, the control and measurement of quantum processors is currently done by systems at room temperature, whose connections to the cryogenic environment present thermal loading that will need to be addressed as these processors scale and their IO requirements to co-processors grow in complexity. As such, one possible path to scaling co-processing capabilities without compromising the quantum processor’s performance is the partial or complete integration of the co-processor in the cryo-environment. Several works describe systems that aim to do just that; and ”Cryo-CMOS” has become an important research subspace. This thesis aims to add to the current advancements in this field, specifically in the area of qubit measurements. It culminates in the implementation of a radio receiver that leverages the advantages of BiCMOS technology in cryo-environments to measure the state of a superconducting transmon-based qubit while strapped to a 4K stage in a dilution refrigerator. Critically, we demonstrate that low-noise amplification, down-conversion, and demodulation can all be done in the cryo-environment on a constrained power budget, with high fidelity comparable to a state-of-the-art (InP-HEMT LNA-based) qubit readout system, when preceded by a high-gain, quantum-noise-limited Josephson parametric amplifier.
High-fidelity single-shot readout of superconducting qubits is essential for fault-tolerant quantum computation. Without a quantum-limited amplifier such as a Josephson parametric amplifier, the cryogenic high-electron-mobility-transistor (HEMT) low-noise amplifier (LNA) at the 4 K stage is the dominant noise source in the readout chain. HEMT LNAs are conventionally characterized by Y-factor measurements of the noise temperature TN, independently of the quantum measurement they ultimately serve. Here we present a qubit-in-the-loop benchmarking method. The method uses the two-dimensional IQ histogram of single-shot readout as a direct figure of merit. We apply it to three state-of-the-art cryogenic InP HEMT LNAs with 53\%, 60\%, and 70\% channel indium content, together with a commercial reference amplifier. The 60\% and 70\% devices have similar TN in Y-factor measurements, both lower than the 53\% device. The 70\% device has the highest gain, but qubit readout SNR and assignment fidelity Fa instead peak at 60\%. Using this method, we map Fa against HEMT LNA dc power consumption for each device. Fa does not simply saturate with increasing power. For several devices it declines above a device-dependent power well below typical operating points. For the 60\% device, which has the highest overall Fa, about 1~mW is needed to maintain Fa>85%. Across all four devices, Fa>80% is reached with as little as about 0.3~mW, roughly an order of magnitude below typical operating points. These results establish a qubit-referenced benchmarking methodology and provide practical guidance for amplifier selection and bias in power-constrained multi-qubit readout systems.