Multiplexed local charge storage, close to quantum processors at cryogenic temperatures could generate a multitude of control signals, for electronics or qubits, in an efficient manner. Such cryogenic electronics require generating quasi-static control signals with small area footprint, low noise, high stability, low power dissipation and, ideally, in a multiplexed fashion to reduce the number of input/outputs. In this work, we integrate capacitors with cryogenic high-electron mobility transistor (HEMT) arrays and demonstrate quasi-static bias generation using gate pulses controlled in time and frequency domains. Multi-channel bias generation is also demonstrated. Operation at 4 K exhibits improved bias signal variability and greatly reduced subthreshold swing, reaching values of ~6 mV/decade. Due to the very low threshold voltage of 80 mV at 4 K and the steep subthreshold swing, these circuits can provide an advantage over the silicon-based complementary metal-oxide-semiconductor equivalents by allowing operation at significantly reduced drive bias in the low output voltage regime <1 V. Together with their high-speed operation, this makes HEMTs an attractive platform for future cryogenic signal generation electronics in quantum computers.
Multiplexed local charge storage, close to quantum processors at cryogenic temperatures could generate a multitude of control signals, for electronics or qubits, in an efficient manner. Such cryogenic electronics require generating quasi-static control signals with small area footprint, low noise, high stability, low power dissipation and, ideally, in a multiplexed fashion to reduce the number of input/outputs. In this work, we integrate capacitors with cryogenic high-electron mobility transistor (HEMT) arrays and demonstrate quasi-static bias generation using gate pulses controlled in time and frequency domains. Multi-channel bias generation is also demonstrated. Operation at 4 K exhibits improved bias signal variability and greatly reduced subthreshold swing, reaching values of ~6 mV/decade. Due to the very low threshold voltage of 80 mV at 4 K and the steep subthreshold swing, these circuits can provide an advantage over the silicon-based complementary metal-oxide-semiconductor equivalents by allowing operation at significantly reduced drive bias in the low output voltage regime <1 V. Together with their high-speed operation, this makes HEMTs an attractive platform for future cryogenic signal generation electronics in quantum computers.
In recent years, quantum computers have emerged as a disruptive technology capable of solving problems currently intractable for classical systems. Computation is performed using qubits, which exploit quantum properties like superposition and entanglement, and requires them to operate at cryogenic temperatures. As a result, quantum computers are built around cryostats that reach temperatures as low as \qty{10}{\milli\kelvin}. However, to deliver a significant advantage over conventional approaches, quantum computers must increase their qubit count, improve qubit quality, and adopt more sophisticated control and readout architectures. The integration of more complex or improved cryogenic electronics inside the cryostat can enhance the scalability of these systems, and is the topic of this thesis. The primary technology platform used in this work is based on cryogenic InGaAs/InP high-electron-mobility transistors (HEMTs). One objective was the development of cryogenic circuits that enhance the scalability of spin-qubit quantum computers by enabling efficient signal delivery in control and readout paths. To this end, cryogenic multiplexers were demonstrated with threshold voltages as low as \qty{90}{\milli\volt}, subthreshold swing of \qty{5}{\milli\volt\per dec}, and on-off ratio of 107 at \qty{4}{\kelvin}. In addition, a charge-storage array was developed for the local generation of qubit bias signals, using an operation scheme based on pulse trains to program voltage levels on capacitors that can be placed in proximity to qubit gates. A second objective was the fabrication of HEMTs with enhanced performance for use in cryogenic low-noise amplifiers, which are critical for qubit readout. Studies were performed to characterize self-heating, an effect that limits transistor performance at cryogenic temperatures. Moreover HEMTs with improved characteristics were fabricated, which achieved exceptional values in state-of-the-art metrics, including fT= \qty{622}{\giga\hertz}, fMAX= \qty{733}{\giga\hertz}, and a noise indication factor IDS/gm= \qty{0.17}{\sqrt{\volt \cdot \milli\meter / \siemens}} at \qty{4}{\kelvin}. These results represent a new record for the combination of high-frequency and low-noise performance in a cryogenic HEMT. These results establish the InGaAs/InP HEMT technology as a promising platform for the development of cryogenic circuits, and demonstrate its versatility in addressing multiple applications requiring both single-device performance and integration at the circuit level.
The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of DC bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this paper presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryo-CMOS demultiplexer and a cryo-CMOS DC DAC have been developed in a 22-nm FinFET process to control a co-developed 2D-array designed with 648 Single Hole Transistors (SHTs). Thanks to the dissipation below 120μW, the whole system operates at temperatures below 70mK in a custom-built electrical/mechanical infrastructure embedded in a standard singlepulse- tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold (S/H) structures, allowing to store 96 unique bias voltages over a 3V range with a voltage drift between 60μV/s and 18 mV/s. This work demonstrates a tight integration at mK-temperatures of cryo- CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors towards the large number of qubits required for a practical quantum computer.
A scaled-up quantum computer will require a highly efficient control interface that autonomously manipulates and reads out large numbers of qubits, which for solid-state implementations are usually held at millikelvin (mK) temperatures. Advanced CMOS technology, tightly integrated with the quantum system, would be ideal for implementing such a control interface but is generally discounted on the basis of its power dissipation that leads to heating of the fragile qubits. Here, we demonstrate an ultra low power, CMOS-based quantum control platform that takes digital commands as input and generates many parallel qubit control signals. Realized using 100,000 transistors operating near 100 mK, our platform alleviates the need for separate control lines to every qubit by exploiting the low leakage of transistors at cryogenic temperatures to store charge on floating gate structures that are used to tune-up quantum devices. This charge can then be rapidly shuffled between on-chip capacitors to generate the fast voltage pulses required for dynamic qubit control. We benchmark this architecture on a quantum dot test device, showing that the control of thousands of gate electrodes is feasible within the cooling power of commercially available dilution refrigerators.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Large-scale qubit readout in quantum computing systems requires highly sensitive amplification with minimal power consumption to reduce the thermal load and preserve qubit integrity. We propose a pulse-operated cryogenic low-noise amplifier (LNA) scheme that minimizes the influence of the LNA on qubit operation and reduces power consumption by duty cycling. A modified commercially available cryogenic hybrid LNA based on InP high-electron mobility transistors (HEMTs) has been characterized to demonstrate the feasibility of pulsed operation for qubit readout. The transient noise and gain performance of the LNA were obtained through a cryogenic time domain noise measurement setup with 5-ns time resolution and a measured noise standard deviation (SD) below 0.3 K. The time-domain noise and gain performance of the LNA in response to a square gate voltage waveform were investigated. Through an analysis of the LNA’s recovery limitations, we developed a fast recovery bias strategy leading to the optimization of the gate voltage waveform using a genetic algorithm (GA). This resulted in a strong enhancement of transient noise and gain performance with a recovery time of 35 ns. The drain current transients were measured to calculate the average power consumption of the pulse-operated LNA, which confirmed a reduction in average power consumption proportional to the duty cycle. This work contributes to the development of high-performance and low-power amplifier solutions critical for large-scale qubit readout applications.
In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.